GATE | GATE-CS-2015 (Set 2) | Question 54

Consider the sequence of machine instructions given below:

  MUL R5, R0, R1
  DIV R6, R2, R3
  ADD R7, R5, R6
  SUB R8, R7, R4 

In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the Result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is ___________

(A)

11

(B)

12

(C)

13

(D)

14

Answer: (C)
Explanation:

  1   2   3   4   5   6   7   8   9   10   11   12   13
  IF  OF  PO  PO  PO  WB
      IF  OF          PO  PO  PO  PO  PO   WB
          IF          OF                   PO   WB
              IF          OF                    PO   WB

It is mentioned in the question that operand forwarding takes place from the PO stage to OF stage and not to the PO stage. So, 15 clock cycles.
But we know that the operand forwarding is from PO-OF, we can do like to make the PO stage produce the output during the rising edge of the clock and OF stage fetch the output during the falling edge. This would mean the final PO stage and OF stage can be done in one clock cycle making the total number of cycles = 13. And 13 is the answer given in the GATE key

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