The adder produce carry propagation delay while performing other arithmetic operations like multiplication and divisions as it uses several additions or subtraction steps. This is a major problem for the adder and hence improving the speed of addition will improve the speed of all other arithmetic operations. Hence reducing the carry propagation delay of adders is of great importance. There are different logic design approaches that have been employed to overcome the carry propagation problem. One widely used approach is to employ a carry look-ahead which solves this problem by calculating the carry signals in advance, based on the input signals. This type of adder circuit is called a carry look-ahead adder.
Here a carry signal will be generated in two cases:
- Input bits A and B are 1
- When one of the two bits is 1 and the carry-in is 1.
In ripple carry adders, for each adder block, the two bits that are to be added are available instantly. However, each adder block waits for the carry to arrive from its previous block. So, it is not possible to generate the sum and carry of any block until the input carry is known. The
Consider the above 4-bit ripple carry adder. The sum
The propagation time is equal to the propagation delay of each adder block, multiplied by the number of adder blocks in the circuit. For example, if each full adder stage has a propagation delay of 20 nanoseconds, then
Carry Look-ahead Adder :
A carry look-ahead adder reduces the propagation delay by introducing more complex hardware. In this design, the ripple carry design is suitably transformed such that the carry logic over fixed groups of bits of the adder is reduced to two-level logic. Let us discuss the design in detail.
Consider the full adder circuit shown above with corresponding truth table. We define two variables as ‘carry generate’
The sum output and carry output can be expressed in terms of carry generate
where
The carry output Boolean function of each stage in a 4 stage carry look-ahead adder can be expressed as
From the above Boolean equations we can observe that
The implementation of three Boolean functions for each carry output (
Time Complexity Analysis :
We could think of a carry look-ahead adder as made up of two “parts”
- The part that computes the carry for each bit.
- The part that adds the input bits and the carry for each bit position.
The
Now, for the generation of the
Advantages and Disadvantages of Carry Look-Ahead Adder :
Advantages –
- The propagation delay is reduced.
- It provides the fastest addition logic.
Disadvantages –
- The Carry Look-ahead adder circuit gets complicated as the number of variables increase.
- The circuit is costlier as it involves more number of hardware.
NOTE :
For n-bit carry lookahead adder to evaluate all the carry bits it requires [n(n + 1)]/2 AND gates and n OR gates.
GATE CS Corner Questions
Practicing the following questions will help you test your knowledge. All questions have been asked in GATE in previous years or in GATE Mock Tests. It is highly recommended that you practice them.
- GATE CS 2016 (Set-1), Question 43
- GATE CS 2004, Question 90
- GATE CS 2007, Question 85
- GATE CS 2006, Question 85
- GATE CS 1997, Question 15
References –
iitkgp.virtual-labs
Carry-lookahead adder – Wikipedia