Which of the following is not true about data transfer using DMA controller.
(A) Bus can be granted to DMA at the end of any phase of instruction execution
(B) If word count is zero DMA will interrupt CPU and CPU will check the status of DMA.
(C) CPU has to wait for completion of an instruction to grant bus to DMA.
(D) DMA transfer is good for fast I/O devices.
Answer: (C)
Explanation:
CPU need not wait for the completion of instruction to grant bus to DMA rather can grant the bus at the end of any phase of instruction execution.
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