Computer Organization and Architecture

Question 21

A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?

• 2 nanoseconds
• 20 nanoseconds
• 22 nanoseconds
• 88 nanoseconds

Question 22

Consider the data from above question. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?

• 222 nanoseconds
• 888 nanoseconds
• 902 nanoseconds
• 968 nanoseconds

Question 23

How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?

• 8
• 32
• 64
• 128

Question 24

Consider a 4 stage pipeline processor.   The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below:

	S1	S2	S3	S4
I1	2	1	1	1
I2	1	3	2	2
I3	2	1	1	3
I4	1	2	2	2

What is the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;}

• 16
• 23
• 28
• 30

Question 25

Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order: 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155. Which one of the following memory block will NOT be in cache if LRU replacement policy is used?

• 3
• 8
• 129
• 216

Question 26

Which of the following is/are true of the auto-increment addressing mode?

I.  It is useful in creating self-relocating code.
II. If it is included in an Instruction Set Architecture, 
    then an additional ALU is required for effective address 
    calculation.
III.The amount of increment depends on the size of the data
     item accessed.

• I only
• II only
• III Only
• II and III only

Question 27

Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor?

I.   It must be a trap instruction
II.  It must be a privileged instruction
III. An exception cannot be allowed to occur during 
     execution of an RFE instruction 

• I only
• II only
• I and II only
• I, II and III only

Question 28

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?

I. L1 must be a write-through cache
II. L2 must be a write-through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache 

• IV only
• I and IV only
• I, III and IV only
• I, II, III and IV

Question 29

Which of the following are NOT true in a pipelined processor?

I.  Bypassing can handle all RAW hazards.
II. Register renaming can eliminate all register 
    carried WAR hazards.
III. Control hazard penalties can be eliminated by 
     dynamic branch prediction.

• I and II only
• I and III only
• II and III only
• I, II and III

Question 30

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for

I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches   

• I only

• II only

• III only

• I, II and III