Computer Organization and Architecture

Question 31

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

• before effective address calculation has started

• during effective address calculation

• after effective address calculation has completed

• after data cache lookup has completed

Question 32

Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins as follows: 

C

double ARR[1024][1024];
int i, j;
// Initialize array ARR to 0.0
for(i = 0; i < 1024; i++)
    for(j = 0; j < 1024; j++)
        ARR[i][j] = 0.0;

The size of double is 8 Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR. The total size of the tags in the cache directory is

• 32 Kbits

• 34 Kbits

• 64 Kbits

• 68 Kbits

Question 33

The cache hit ratio for this initialization loop is

• 0%
• 25%
• 50%
• 75%

Question 34

Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields arerespectively:

• 9,6,5

• 7, 7, 6

• 7, 5, 8

• 9, 5, 6

Question 35

Consider a pipelined processor with the following four stages:

IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage dependson the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

ADD R2, R1, R0       R2 <- R0 + R1
MUL R4, R3, R2       R4 <- R3 * R2
SUB R6, R5, R4       R6 <- R5 - R4  

• 7
• 8
• 10
• 14

Question 36

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

• 10
• 11
• 20
• 21

Question 37

Consider the data given in above question. Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

• 100
• 101
• 102
• 110

Question 38

Consider the data given in above questions. Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?

• 1005
• 1020
• 1024
• 1040

Question 39

Consider a machine with a byte addressable main memory of 2¹⁶ bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 × 50 two-dimensional array of bytes is stored in the main memory starting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses. How many data cache misses will occur in total?

• 40
• 50
• 56
• 59

Question 40

Consider the data given in above question. Which of the following lines of the data cache will be replaced by new blocks in accessing the array for the second time?

• line 4 to line 11
• line 4 to line 12
• line 0 to line 7
• line 0 to line 8