Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a
pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls
in the pipeline. The speedup achieved in this pipelined processor is
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a
sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively:
Let the page fault service time be 10 ms in a computer with average memory access time being 20 ns. If one page fault is generated for every
106 memory accesses, what is the effective access time for the memory?