ISRO CS 2009

Question 21

Suppose the numbers 7, 5, 1, 8, 3, 6, 0, 9, 4, 2 are inserted in that order into an initially empty binary search tree. The binary search tree uses the usual ordering on natural numbers. What is the inorder traversal sequence of the resultant tree?

• 7 5 1 0 3 2 4 6 8 9
• 0 2 4 3 1 6 5 9 8 7
• 0 1 2 3 4 5 6 7 8 9
• 9 8 6 4 2 3 0 1 5 7

Question 22

A data structure is required for storing a set of integers such that each of the following operations can be done in O(log n) time, where n is the number of elements in the set. I. Deletion of the smallest element II. Insertion of an element if it is not already present in the set Which of the following data structures can be used for this purpose?

• A heap can be used but not a balanced binary search tree
• A balanced binary search tree can be used but not a heap
• Both balanced binary search tree and heap can be used
• Neither balanced search tree nor heap can be used

Question 23

Assume that the operators +, −, × are left associative and ^ is right associative. The order of precedence (from highest to lowest) is ^, ×, +, −. The postfix expression corresponding to the infix expression is

a + b × c − d ^ e ^ f

• abc x + def ^ ^ −
• abc x + de ^ f ^ −
• ab + c × d − e^f^
• − + a × b c^^ def

Question 24

The expression 1 * 2 ^ 3 * 4 ^ 5 * 6 will be evaluated as

• 32³⁰
• 162³⁰
• 49152
• 173458

Question 25

The feature in object-oriented programming that allows the same operation to be carried out differently, depending on the object, is:

• Inheritance
• Polymorphism
• Overfunctioning
• Overriding

Question 26

The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words

• 10, 3, 1024
• 8, 5, 256
• 5, 8, 2048
• 10, 3, 512

Question 27

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

• 400
• 500
• 600
• 700

Question 28

Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stores in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively

• 256 Mbyte, 19 bits
• 256 Mbyte, 28 bit
• 512 Mbyte, 20 bits
• 64 Gbyte, 28 bits

Question 29

Consider a pipelined processor with the following four stages:

IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

ADD       R2, R1, R0        R2 ← R1 + R0
MUL       R4, R3, R2        R4 ← R3 * R2
SUB       R6, R5, R4        R6 ← R5 - R4

• 7
• 8
• 10
• 14

Question 30

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for I. Function locals and parameters II. Register saves and restores III. Instruction fetches

• I only
• II only
• III only
• I, II and III