Sequential circuits

Question 11

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

• Q = 0, Q\' = 1

• Q = 1, Q\' = 0

• Q = 1, Q\' = 1

• Indeterminate states

Question 12

The next state table of a 2 bit saturating up-counter is given below. The counter is built as synchronous sequential circuit using D flip-flops. The value for D₁ and D₂ are

• D₁ = Q₀ + Q₁ D₂ = Q\'₀ + Q₁

• D₁ = Q\'₁Q₀ D₂ = Q\'₁ + Q\'₀

• D₁ = Q\'₀ + Q₁ D₂ = Q₀ + Q₁

• None of these

Question 13

Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-0, as shown below 

[caption width="800"] [/caption]

To complete the circuit, the input X should be

• Q2\'

• Q2 + Q1

• (Q1 ⊕ Q2)\'

• Q1 ⊕ Q2

Question 14

A 1-input, 2-output synchronous sequential circuit behaves as follows : Let zk, nk denote the number of 0\'s and 1\'s respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds.

    zk - nk = 2. In this case, the output at the k-th and 
                 all subsequent clock ticks is 10.
    nk - zk = 2. In this case, the output at the k-th and
                 all subsequent clock ticks is 01.

What is the minimum number of states required in the state transition graph of the above circuit?

• 5

• 6

• 7

• 8

Question 15

Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0. Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y? [caption width="800"] [/caption]

• a

• b

• c

• d

Question 16

Consider the circuit given below with initial state Q0 =1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the correct state sequence of the circuit?

• 1,3,4,6,7,5,2

• 1,2,5,3,7,6,4

• 1,2,7,3,5,6,4

• 1,6,5,7,2,3,4

Question 17

The following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (re­spectively),

• 1, 0

• 1, 1

• 0, 0

• 0,1

Question 18

Consider a 4 bit Johnson counter with an initial value of 0000. The counting sequence of this counter is:

• 0, 1, 3, 7, 15, 14, 12, 8, 0

• 0, 1, 3, 5, 7, 9, 11, 13, 15, 0

• 0, 2, 4, 6, 8, 10, 12, 14, 0

• 0, 8, 12, 14, 15, 7, 3, 1, 0

Question 19

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

• 0110110...

• 0100100...

• 011101110...

• 011001100...

Question 20

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,...) is ________

• 0

• 1

• 2

• 3