Secondary memory and DMA

Last Updated : 19 Nov, 2018
Question 1

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.

              Initialize the address register
              Initialize the count to 500
        LOOP: Load a byte from device
              Store in memory at address given by address register
              Increment the address register
              Decrement the count
              If count != 0 go to LOOP 

Assume that each statement in this program is equivalent to machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?

Tick

3.4

Cross

4.4

Cross

5.1

Cross

6.7



Question 1-Explanation: 
 Explanation:
                        STATEMENT                                           CLOCK CYCLE(S) NEEDED
              Initialize the address register                                        1
              Initialize the count to 500                                            1
        LOOP: Load a byte from device                                                2
              Store in memory at address given by address register                   2
              Increment the address register                                         1
              Decrement the count                                                    1
              If count != 0 go to LOOP                                               1

        Interrupt driven transfer time = 1+1+500×(2+2+1+1+1) = 3502
        DMA based transfer time = 20+500*2 = 1020
        Speedup = 3502/1020 ≈ 3.4

Source: http://clweb.csa.iisc.ernet.in/rahulsharma/gate2011key.html
Question 2

In a computer system, four files of size 11050 bytes, 4990 bytes, 5170 bytes and 12640 bytes need to be stored. For storing these files on disk, we can use either 100 byte disk blocks or 200 byte disk blocks (but can't mix block sizes). For each block used to store a file, 4 bytes of bookkeeping information also needs to be stored on the disk. Thus, the total space used to store a file is the sum of the space taken to store the file and the space taken to store the book keeping information for the blocks allocated for storing the file. A disk block can store either bookkeeping information for a file or data from a file, but not both. What is the total space required for storing the files using 100 byte disk blocks and 200 byte disk blocks respectively?

Cross

35400 and 35800 bytes

Cross

35800 and 35400 bytes

Tick

35600 and 35400 bytes

Cross

35400 and 35600 bytes



Question 2-Explanation: 


Using 100 bytes disk blocks : 
1. File of size 11050 bytes Blocks required to store data = 11050/100 = 111 Blocks required for bookkeeping = (111 * 4)/100 = 5 Total blocks = 111 + 5 = 116 
2. File of size 4990 bytes Blocks required to store data = 4990/100 = 50 Blocks required for bookkeeping = (50 * 4)/100 = 2 Total blocks = 50 + 2 = 52 
3. File of size 5170 bytes Blocks required to store data = 5170/100 = 52 Blocks required for bookkeeping = (52 * 4)/100 = 3 Total blocks = 52 + 3 = 55 
4. File of size 12640 bytes Blocks required to store data = 12640/100 = 127 Blocks required for bookkeeping = (127 * 4)/100 = 6 Total blocks = 127 + 6 = 133 
Total space required for storing the files using 100 byte disk blocks = (116 + 52 + 55 + 133) * 100 = 35600 bytes 
 
Using 200 bytes disk blocks : 
1. File of size 11050 bytes Blocks required to store data = 11050/200 = 56 Blocks required for bookkeeping = (56 * 4)/200 = 2 Total blocks = 56 + 2 = 58 
2. File of size 4990 bytes Blocks required to store data = 4990/200 = 25 Blocks required for bookkeeping = (25 * 4)/200 = 1 Total blocks = 25 + 1 = 26 
3. File of size 5170 bytes Blocks required to store data = 5170/200 = 26 Blocks required for bookkeeping = (26 * 4)/200 = 1 Total blocks = 26 + 1 = 27 
4. File of size 12640 bytes Blocks required to store data = 12640/200 = 64 Blocks required for bookkeeping = (64 * 4)/200 = 2 Total blocks = 64 + 2 = 66 
Total space required for storing the files using 200 byte disk blocks = (58 + 26 + 27 + 66) * 200 = 35400 bytes 
 
Thus, option (C) is correct. 

Question 3
The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________   Note : This question was asked as Numerical Answer Type.
Cross
3644
Cross
3645
Tick
456
Cross
1823


Question 3-Explanation: 
Size of data count register of the DMA controller = 16 bits Data that can be transferred in one go = 216 bytes = 64 kilobytes File size to be transferred = 29154 kilobytes So, number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory = ceil(29154/64) = 456   Thus, C is the correct answer.
Question 4

Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?  

Cross

Transparent DMA and Polling interrupts

Cross

Cycle-stealing and Vectored interrupts

Tick

Block transfer and Vectored interrupts

Cross

Block transfer and Polling interrupts



Question 4-Explanation: 

Among the options provided, the DMA transfer mode and interrupt handling mechanism that enable the highest I/O bandwidth is option (C): Block transfer and Vectored interrupts.

Let's understand why this choice provides the highest I/O bandwidth:

  1. Transparent DMA: Transparent DMA is not the most efficient option for achieving high I/O bandwidth. It allows the DMA controller to directly access the memory and transfer data without CPU involvement. However, it doesn't utilize interrupts effectively for signaling completion or handling data transfer events.
  2. Cycle-stealing: Cycle-stealing DMA interrupts the CPU during its normal operation to transfer data. While it can improve I/O bandwidth, it interrupts the CPU frequently, affecting its performance.
  3. Block transfer: Block transfer DMA involves transferring a block of data in a single operation. It minimizes the number of interrupts needed for transferring large amounts of data, resulting in efficient data transfer.
  4. Polling interrupts: Polling interrupts require the CPU to check the status of the DMA controller repeatedly to determine if data transfer has completed. This approach involves continuous CPU involvement and wastes CPU cycles, making it less efficient for achieving high I/O bandwidth.
  5. Vectored interrupts: Vectored interrupts allow the DMA controller to directly inform the CPU about data transfer events, reducing the CPU overhead. The CPU can efficiently handle the interrupts and resume its normal operations.

Considering the characteristics described above, option (C) combines block transfer DMA, which minimizes interrupts for large data transfers, with vectored interrupts, which efficiently notify the CPU about data transfer events. This combination maximizes the I/O bandwidth by reducing CPU involvement and efficiently utilizing interrupts, making it the best choice among the provided options for achieving the highest I/O bandwidth.

Question 5
Which of the following systems is a most likely candidate example of a pipe and filter architecture ?
Cross
Expert system
Cross
DB repository
Cross
Aircraft flight controller
Tick
Signal processing


Question 5-Explanation: 
Pipe and Filters In the pipes and filters pattern, components are filters and connectors are pipes. Each filter takes input insome form and produces output in some other form, which may or may not be similar to the input form.Hopefully,each filter will add value to the output stream because of processing done inside the filter. Each filter is independent and is unaware of the up and down stream filters. Pipes are conduits of the data streams. Famous example of the pipes and filters architectural pattern are UNIX shells,signal processing systems and distributed systems.
Reference: Software Architecture: A Case Based Approach By Vasudeva Varma, Varma Vasudeva
Question 6
The main difference(s) between a CISC and a RISC processor is/are that a USC processor typically: a) has fewer instructions b) has fewer addressing modes c) has more registers d) is easier to implement using hardwired control logic
Cross
a and b
Cross
b and c
Cross
a and d
Tick
a, b, c and d


Question 7
The address space of 8086 CPU is
Tick
One Megabyte
Cross
256 Kilobytes
Cross
1 K Megabytes
Cross
64 Kilobytes


Question 8
If an instruction takes i microseconds and a page fault takes an additional j microseconds, the effective instruction time if on the average a  page fault occurs every k instructions is:
Tick
i + j/k
Cross
i + j* k
Cross
(i + j)/ k
Cross
(i + j)* k


Question 9
The correct matching for the following pairs is
(A) DMA I/O                    (1) High speed RAM
(B) Cache                      (2) Disk
(C) Interrupt I/O              (3) Printer
(D) Condition Code Register    (4) ALU
Codes:
    A   B   C   D 
a   4   3   1   2
b   2   1   3   4
c   4   3   2   1
d   2   3   4   1
Cross
a
Tick
b
Cross
c
Cross
d


Question 10
For the daisy chain scheme of connecting I/O devices, which of the following statement is true?
Tick
It gives non-uniform priority to various devices
Cross
It gives uniform priority to all devices
Cross
It is only useful for connecting slow devices to a processor
Cross
It requires a separate interrupt pin on the processor for each device


There are 23 questions to complete.

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