Secondary memory and DMA

Question 11

For the daisy chain scheme of connecting I/O devices, which of the following statement is true?

• It gives non-uniform priority to various devices
• It gives uniform priority to all devices
• It is only useful for connecting slow devices to a processor
• It requires a separate interrupt pin on the processor for each device

Question 12

A micro program control unit is required to generate a total of 25 control signals. Assume that during any microinstruction , at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be

• 2

• 2.5

• 10

• 12

Question 13

A hard disk is connected to a 50 MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes 1000 clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires 500 clock cycles for the processor. The hard disk has a transfer rate of 2000 Kbytes/sec and average block transferred is 4 K bytes. What fraction of the processor time is consumed by the disk, if the disk is actively transferring 100% of the time?  

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           .

• 1.5%

• 1%

• 2.5%

• 10%

Question 14

A 32 - bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2¹⁴. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _______ . Note - This was Numerical Type question.

• 59
• 40
• 99
• None of these

Question 15

The number of logical CPUs in a computer having two physical quad-core chips with hyper threading enabled is

• 1
• 2
• 8
• 16

Question 16

If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 x 6 array, where each chip is 8K x 4 bits ?

• 13
• 15
• 16
• 17

Question 17

In DMA transfer scheme, the transfer scheme other than burst mode is

• cycle technique
• stealing technique
• cycle stealing technique
• cycle bypass technique

Question 18

Which of the following statements about synchronous and asynchronous I/O is NOT true?

• An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O

• In both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is invoked after completion of the I/O

• A process making a synchronous I/O call waits until I/O is complete, but a process making an asynchronous I/O call does not wait for completion of the I/O

• In the case of synchronous I/O, the process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O

Question 19

The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words

• 10, 3, 1024
• 8, 5, 256
• 5, 8, 2048
• 10, 3, 512

Question 20

In comparison with static RAM memory, the dynamic Ram memory has

• lower bit density and higher power consumption
• higher bit density and higher power consumption
• lower bit density and lower power consumption
• higher bit density and lower power consumption