GATE-CS-2005

Question 61

Consider line number 3 of the following C- program. 

C

int main ( ) {                   /* Line 1 */
  int I, N;                      /* Line 2 */
  fro (I = 0, I < N, I++);       /* Line 3 */
}

Identify the compiler\'s response about this line while creating the object-module

• No compilation error

• Only a lexical error

• Only syntactic errors

• Both lexical and syntactic errors

Question 62

Consider the following circuit involving a positive edge triggered D FF.

Consider the following timing diagram. 
Let Ai represent the logic level on the line A in the i-th clock period. 
 Let A\' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is

• A0 Al A1\' A3 A4

• A0 Al A2\' A3 A4

• Al A2 A2\' A3 A4

• Al A2\' A3 A4 A5\'

Question 63

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit. Which one of the following is TRUE?

• It computes 1\'s complement of the input number
• It computes 2\'s complement of the input number
• It increments the input number
• It decrements the input number

Question 64

Consider the following circuit.

The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:

 A)  
B) 
C)
D)

• A

• B

• C

• D

Question 65

Consider a three word machine instruction

ADD A[R0], @ B 

The first operand (destination) "A [R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is

• 3
• 4
• 5
• 6

Question 66

Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.

 1 A[1] = B[J];	     a Indirect addressing
 2 while [*A++];     b Indexed, addressing
 3 int temp = *x;    c Autoincrement 

• (1, c), (2, b), (3, a)
• (1, a), (2, c), (3, b)
• (1, b), (2, c), (3, a)
• (1, a), (2, b), (3, c)

Question 67

Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively

• 10, 17
• 10, 22
• 15, 17
• 5, 17

Question 68

A 5 stage pipelined CPU has the following sequence of stages:

IF — Instruction fetch from instruction memory,
RD — Instruction decode and register read,
EX — Execute: ALU operation for data and address computation,
MA — Data memory access - for write access, the register read
     at RD stage is used,
WB — Register write back.
Consider the following sequence of instructions:
I1 : L R0, 1oc1;        R0 <= M[1oc1]
I2 : A R0, R0;           R0 <= R0 + R0
I3 : S R2, R0;           R2 <= R2 - R0
Let each stage take one clock cycle.

What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1 ?

• 8

• 10

• 12

• 15

Question 69

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 microsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

• 15
• 25
• 35
• 45

Question 70

Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:

• 10
• 25
• 40
• 50