GATE-CS-2004

Question 61

Directions for question 63 to 64: Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

 Instruction 	 Operation 	 Instruction Size(in words)
 MOV R1,5000; 	 R1 ¬ Memory[5000] 	 2
 MOV R2, (R1); 	 R2 ¬ Memory[(R1)] 	 1
 ADD R2, R3; 	 R2 ¬ R2 + R3 	         1
 MOV 6000, R2; 	 Memory [6000] ¬ R2 	 2
 HALT 	         Machine halts 	         1

Let the clock cycles required for various operations be as follows: Register to/ from memory transfer: 3 clock cycles ADD with both operands in register : 1 clock cycle Instruction fetch and decode : 2 clock cycles per word The total number of clock cycles required to execute the program is

• 29

• 24

• 23

• 20

Question 62

Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is 8, 12, 0, 12, 8

• 2
• 3
• 4
• 5

Question 63

The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

• 10, 3, 1024
• 8, 5, 256
• 5, 8, 2048
• 10, 3, 512

Question 64

A hard disk with a transfer rate of 10 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 600 MHz, and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes, what is the percentage of processor time consumed for the transfer operation ?

• 5.0%
• 1.0%
• 0.5%
• 0.1%

Question 65

Let A = 1111 1010 arid B = 0000 1010 be two 8-bit 2\'s complement numbers. Their product in 2\'s complement is

• 1100 0100
• 1001 1100
• 1010 0101
• 1101 0101

Question 66

A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

• 120.4 microseconds
• 160.5 microseconds
• 165.5 microseconds
• 590.0 microseconds

Question 67

The following propositional statement is 
(P → (Q v R)) → ((P ^ Q) → R)

• satisfiable but not valid
  

• valid
  

• a contradiction
  

• none of the above
  

Question 68

How many solutions does the following system of linear equations have ? 

  -x + 5y = -1
   x - y = 2
   x + 3y = 3

• unique
  

• two distinct solutions
  

• infinitely many
  

• none of these
  

Question 69

The following is the incomplete operation table a 4-element group. 

 *
 e
 a
 b
 c


 e
 e
 a
 b
 c


 a
 a
 b
 c
 e


 b






 c

The last row of the table is

• c a e b 
  
  
  

• c b a e
  

• c b e a
  

• c e a b
  

Question 70

The inclusion of which of the following sets into 

S = {{1, 2}, {1, 2, 3}, {1, 3, 5}, (1, 2, 4), (1, 2, 3, 4, 5}}

is necessary and sufficient to make S a complete lattice under the partial order defined by set containment ?

• {1}, {1, 3}
  

• {1}, {2, 3}
  

• {1}
  

• {1}, {1, 3}, (1, 2, 3, 4}, {1, 2, 3, 5)