Which of the following page replacement algorithms suffers from Belady’s anomaly?
Optimal Page Replacement
Both LRU and FIFO
What is the swap space in the disk used for?
Saving temporary html pages
Saving process data
Storing the super-block
Storing device drivers
Question 2 Explanation:
Swap space is typically used to store process data. See this for more details.
Increasing the RAM of a computer typically improves performance because:
Virtual memory increases
Larger RAMs are faster
Fewer page faults occur
Fewer segmentation faults occur
Question 3 Explanation:
When there is more RAM, there would be more mapped virtual pages in physical memory, hence fewer page faults. A page fault causes performance degradation as the page has to be loaded from secondary device.
A computer system supports 32-bit virtual addresses as well as 32-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to get rid of the virtual memory entirely. Which one of the following is true?
Efficient implementation of multi-user support is no longer possible
The processor cache organization can be made more efficient now
Hardware support for memory management is no longer needed
CPU scheduling can be made more efficient now
Question 4 Explanation:
For supporting virtual memory, special hardware support is needed from Memory Management Unit. Since operating system designers decide to get rid of the virtual memory entirely, hardware support for memory management is no longer needed
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
Question 5 Explanation:
Size of a page = 4KB = 2^12 Total number of bits needed to address a page frame = 32 – 12 = 20 If there are ‘n’ cache lines in a set, the cache placement is called n-way set associative. Since TLB is 4 way set associative and can hold total 128 (2^7) page table entries, number of sets in cache = 2^7/4 = 2^5. So 5 bits are needed to address a set, and 15 (20 – 5) bits are needed for tag.
Virtual memory is
Large secondary memory
Large main memory
Illusion of large main memory
None of the above
Question 6 Explanation:
Virtual memory is illusion of large main memory.
Page fault occurs when
When a requested page is in memory
When a requested page is not in memory
When a page is currupted
When an exception is thrown
Question 7 Explanation:
Page fault occurs when a requested page is mapped in virtual address space but not present in memory.
Thrashing occurs when
When a page fault occurs
Processes on system frequently access pages not memory
Processes on system are in running state
Processes on system are in waiting state
Question 8 Explanation:
Thrashing occurs processes on system require more memory than it has. If processes do not have “enough” pages, the pagefault rate is very high. This leads to: – low CPU utilization – operating system spends most of its time swapping to disk The above situation is called thrashing
A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer? (GATE 2013)
Question 9 Explanation:
Let the page size is of 'x' bits Size of T1 = 2 ^ x bytes (This is because T1 occupies exactly one page) Now, number of entries in T1 = (2^x) / 4 (This is because each page table entry is 32 bits or 4 bytes in size) Number of entries in T1 = Number of second level page tables (Because each I-level page table entry stores the base address of page of II-level page table) Total size of second level page tables = ((2^x) / 4) * (2^x) Similarly, number of entries in II-level page tables = Number of III level page tables = ((2^x) / 4) * ((2^x) / 4) Total size of third level page tables = ((2^x) / 4) * ((2^x) / 4) * (2^x) Similarly, total number of entries (pages) in all III-level page tables = ((2^x) / 4) * ((2^x) / 4) * ((2^x) / 4) = 2^(3x - 6) Size of virtual memory = 2^46 Number of pages in virtual memory = (2^46) / (2^x) = 2^(46 - x) Total number the pages in the III-level page tables = Number of pages in virtual memory 2^(3x - 6) = 2^(46 - x) 3x - 6 = 46 - x 4x = 52 x = 13 That means, page size is of 13 bits or Page size = 2^13 bytes = 8 KB
Consider data given in the above question. What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer? (GATE CS 2013)
Question 10 Explanation:
1 MB 16-way set associative virtually indexed physically tagged cache(VIPT). The cache block size is 64 bytes. No of blocks is 2^20/2^6 = 2^14. No of sets is 2^14/2^4 = 2^10. VA(46) +-------------------------------+ tag(30) , Set(10) , block offset(6) +-------------------------------+ In VIPT if the no. of bits of page offset = (Set+block offset) then only one page color is sufficient. but we need 8 colors because the number bits where the cache set index and physical page number over lap is 3 so 2^3 page colors is required.(option c is ans).
There are 148 questions to complete.
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