CPU control design and Interfaces

Question 1

Consider the following statements.

• I. Daisy chaining is used to assign priorities in attending interrupts.
• II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.
• III. In polling,the CPU periodically checks the status bits to know if any device needs its attention.
• IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE ?

• Ⅰ and Ⅱ only
• Ⅰ and Ⅳ only
• Ⅰ and Ⅲ only
• Ⅲ only

Question 2

Consider the following data path diagram. Consider an instruction:

R0 ← R1 + R2 

The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

1. R2_r, TEMP1_r, ALU_add, TEMP2_w
2. R1_r, TEMP1_w
3. PC_r, MAR_w, MEM_r
4. TEMP2_r, R0_w
5. MDR_r, IR_w

Which one of the following is the correct order of execution of the above steps ?

• 2, 1, 4, 5, 3
• 1, 2, 4, 3, 5
• 3, 5, 2, 1, 4
• 3, 5, 1, 2, 4

Question 3

The amount of ROM needed to implement a 4 bit multiplier is

• 64 bits
• 128 bits
• 1 Kbits
• 2 Kbits

Question 4

Consider the following sequence of micro-operations.

     MBR ← PC 
     MAR ← X  
     PC ← Y  
     Memory ← MBR

Which one of the following is a possible operation performed by this sequence?

• Instruction fetch
• Operand fetch
• Conditional branch
• Initiation of interrupt service

Question 5

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for

I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches   

• I only

• II only

• III only

• I, II and III

Question 6

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________

• 1000

• 10000

• 100000

• 100

Question 7

Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

• Neither vectored interrupt nor multiple interrupting devices are possible.

• Vectored interrupts are not possible but multiple interrupting devices are possible.

• Vectored interrupts and multiple interrupting devices are both possible.

• Vectored interrupt is possible but multiple in­terrupting devices are not possible.

Question 8

Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where = A or B, has the specification
M [SP] ← r
SP ← SP – 1
How many CPU clock cycles are needed to execute the “push r” instruction?

• 1

• 3

• 4

• 5

Question 9

What is the minimum size of ROM required to store the complete truth table of an 8-bit x 8-bit multiplier?

• 32 K x 16 bits
• 64 K x 16 bits
• 16 K x 32 bits
• 64 K x 32 bits

Question 10

A CPU has only three instructions I1, I2 and I3, which use the following signals in time steps T1-T5: I1 : T1 : Ain, Bout, Cin T2 : PCout, Bin T3 : Zout, Ain T4 : Bin, Cout T5 : End I2 : T1 : Cin, Bout, Din T2 : Aout, Bin T3 : Zout, Ain T4 : Bin, Cout T5 : End I3 : T1 : Din, Aout T2 : Ain, Bout T3 : Zout, Ain T4 : Dout, Ain T5 : End Which of the following logic functions will generate the hardwired control for the signal Ain ?

• T1.I1 + T2.I3 + T4.I3 + T3
• (T1 + T2 + T3).I3 + T1.I1
• (T1 + T2 ).I1 + (T2 + T4).I3 + T3
• (T1 + T2 ).I2 + (T1 + T3).I1 + T3