CPU control design and Interfaces

Question 1
Consider the following sequence of micro-operations.
     MBR ← PC 
     MAR ← X  
     PC ← Y  
     Memory ← MBR
Which one of the following is a possible operation performed by this sequence?
Instruction fetch
Operand fetch
Conditional branch
Initiation of interrupt service

Question 1-Explanation: 
MBR - Memory Buffer Register ( that stores the data being transferred to and from the immediate access store) MAR - Memory Address Register ( that holds the memory location of data that needs to be accessed.) PC - Program Counter ( It contains the address of the instruction being executed at the current time ) The 1st instruction places the value of PC into MBR The 2nd instruction places an address X into MAR. The 3rd instruction places an address Y into PC. The 4th instruction places the value of MBR ( which was the old PC value) into Memory. Now it can be seen from the 1st and the 4th instructions, that the control flow was not sequential and the value of PC was stored in the memory, so that the control can again come back to the address where it left the execution. This behavior is seen in the case of interrupt handling. And here X can be the address of the location in the memory which contains the beginning address of Interrupt service routine. And Y can be the beginning address of Interrupt service routine. In case of conditional branch (as for option C ) only PC is updated with the target address and there is no need to store the old PC value into the memory. And in the case of Instruction fetch and operand fetch ( as for option A and B), PC value is not stored anywhere else. Hence option D.
Question 2
The amount of ROM needed to implement a 4 bit multiplier is
64 bits
128 bits
1 Kbits
2 Kbits

Question 2-Explanation: 
For a 4 bit multiplier, there are 24 * 24 combinations, i.e., 28 combinations. Also, Output of a 4 bit multiplier is 8 bits. Thus, the amount of ROM needed = 28 * 8 = 211 = 2048 bits = 2Kbits
Question 3

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for

I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches   

I only


II only


III only


I, II and III

Question 3-Explanation: 

I is true as by using multiple register windows, we eliminate the need to access the variable values again and again from the memory. Rather, we store them in the registers. 

II is false as register saves and restores would still be required for each and every variable. 

III is also false as instruction fetch is not affected by memory access using multiple register windows. 

So, only I is true. Hence, A is the correct option. 

Question 4

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________









Question 4-Explanation: 

One request initiation takes 100 ns. As the operations of memory module may overlap in time another, request can be initiated before it completes its remaining 500 ns. Thus total requests that can be initiated is 1000000 ns/100 ns =10000.

Question 5

Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?


Neither vectored interrupt nor multiple interrupting devices are possible.


Vectored interrupts are not possible but multiple interrupting devices are possible.


Vectored interrupts and multiple interrupting devices are both possible.


Vectored interrupt is possible but multiple in­terrupting devices are not possible.

Question 5-Explanation: 

It depends on CPU.

Question 6

Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where = A or B, has the specification
M [SP] ← r
SP ← SP – 1
How many CPU clock cycles are needed to execute the “push r” instruction?









Question 6-Explanation: 

SP out, MAR in ------ 2 cycles as they are 16 bit and system bus is of 8 bits

A out, MDR in --------- 1 cycle

M[MAR]<----- MDR ------- 2 cycles

So total 5 cycles,
option D is the correct answer

Question 7
What is the minimum size of ROM required to store the complete truth table of an 8-bit x 8-bit multiplier?
32 K x 16 bits
64 K x 16 bits
16 K x 32 bits
64 K x 32 bits

Question 7-Explanation: 
Input to ROM - 2 lines ,8 bit each. Possible combinations in ROM - (2^8)x(2^8) Size of truth table = (2^8)*(2^8)=2^16=64 KB Maximum output size = 16 bit So, Answer is B
Question 8
A CPU has only three instructions I1, I2 and I3, which use the following signals in time steps T1-T5: I1 : T1 : Ain, Bout, Cin T2 : PCout, Bin T3 : Zout, Ain T4 : Bin, Cout T5 : End I2 : T1 : Cin, Bout, Din T2 : Aout, Bin T3 : Zout, Ain T4 : Bin, Cout T5 : End I3 : T1 : Din, Aout T2 : Ain, Bout T3 : Zout, Ain T4 : Dout, Ain T5 : End Which of the following logic functions will generate the hardwired control for the signal Ain ?
T1.I1 + T2.I3 + T4.I3 + T3
(T1 + T2 + T3).I3 + T1.I1
(T1 + T2 ).I1 + (T2 + T4).I3 + T3
(T1 + T2 ).I2 + (T1 + T3).I1 + T3

Question 9
A hardwired CPU uses 10 control signals S1 to S10, in various time steps T1 to T5, to implement 4 instructions I1 to I4 as shown below: table Which of the following pairs of expressions represent the circuit for generating control signals S5 and S10 respectively? ((Ij+Ik)Tn indicates that the control signal should be generated in time step Tn if the instruction being executed is Ij or lk)  
S5=T1+I2⋅T3 and S10=(I1+I3)⋅T4+(I2+I4)⋅T5
S5=T1+(I2+I4)⋅T3 and S10=(I1+I3)⋅T4+(I2+I4)⋅T5
S5=T1+(I2+I4)⋅T3 and S10=(I2+I3+I4)⋅T2+(I1+I3)⋅T4+(I2+I4)⋅T5
S5=T1+(I2+I4)⋅T3 and S10=(I2+I3)⋅T2+I4⋅T3+(I1+I3)⋅T4+(I2+I4)⋅T5

Question 10
n instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as follows:
Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.
How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming?








Question 10-Explanation: 

In horizontal microprogramming, each control signal is represented by one bit in the microinstruction. Therefore, total number of bits of the control words required in Horizontal microprogramming : = 20 + 70 + 2 + 10 + 23 = 125 bits 
In vertical microprogramming, 'n' control signals encoded into log2 n bits. group 1 : log2 20 = 5 bits group 2 : log2 70 = 7 bits group 3 : log2 2 = 1 bits group 4 : log2 10 = 4 bits group 5 : log2 23 = 5 bits 
Total number of bits required in vertical microprogramming = 5 + 7 + 1 + 4 + 5 = 22 bits 
So, number of bits saved= 125 - 22 = 103 bits. 
Thus, option (B) is correct. 

There are 39 questions to complete.

  • Last Updated : 19 Nov, 2018

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