CPU control design and Interfaces

Question 11

A hardwired CPU uses 10 control signals S1 to S10, in various time steps T1 to T5, to implement 4 instructions I1 to I4 as shown below: Which of the following pairs of expressions represent the circuit for generating control signals S5 and S10 respectively? ((Ij+Ik)Tn indicates that the control signal should be generated in time step Tn if the instruction being executed is Ij or lk)  

• S5=T1+I2⋅T3 and S10=(I1+I3)⋅T4+(I2+I4)⋅T5
• S5=T1+(I2+I4)⋅T3 and S10=(I1+I3)⋅T4+(I2+I4)⋅T5
• S5=T1+(I2+I4)⋅T3 and S10=(I2+I3+I4)⋅T2+(I1+I3)⋅T4+(I2+I4)⋅T5
• S5=T1+(I2+I4)⋅T3 and S10=(I2+I3)⋅T2+I4⋅T3+(I1+I3)⋅T4+(I2+I4)⋅T5

Question 12

n instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as follows:

Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.

How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming?

• 0

• 103

• 22

• 55

Question 13

Consider a CPU where all the instructions require 7 clock cycles to complete execution. There are 140 instructions in the instruction set. It is found that 125 control signals are needed to be generated by the control unit. While designing the horizontal microprogrammed control unit, single address field format is used for branch control logic. What is the minimum size of the control word and control address register?

• 125, 7

• 125, 10

• 135, 7

• 135, 10

Question 14

Arrange the following configurations for CPU in decreasing order of operating speeds; Hardwired Control, vertical microprogramming, horizontal microprogramming

• Hardwired control, Vertical microprogramming, Horizontal microprogramming.

• Hardwired control, Horizontal microprogramming, Vertical microprogramming.

• Horizontal microprogramming, Vertical microprogramming, Hardwired control.

• Vertical microprogramming, Horizontal microprogramming, Hardwired control.

Question 15

Which of the following is true?

• Unless enabled, a CPU will not be able to process interrupts.
• Loop instructions cannot be interrupted till they complete.
• A processor checks for interrupts before executing a new instruction.
• Only level triggered interrupts are possible in microprocessors.

Question 16

RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routine from interrupt vector location

• 0000H
• 0075H
• 003CH
• 0034H

Question 17

In Distributed system, the capacity of a system to adapt the increased service load is called __________ .

• Tolerance
• Scalability
• Capability
• Loading

Question 18

Which of the following Super Computers is the fastest Super Computer ?

• Sun-way TaihuLight
• Titan
• Piz Daint
• Sequoia

Question 19

Which speed up could be achieved according to Amdahl’s Law for infinite number of processes if 5% of a program is sequential and the remaining part is ideally parallel ?

• Infinite
• 5
• 20
• 50

Question 20

Which of the following is correct statement ?

• In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words.
• The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.
• In asynchronous serial transfer of data the two units share a common clock.
• In synchronous serial transmission of data the two units have different clocks.