Computer Organization and Architecture

Question 211

The Memory Address Register

• is a hardware memory device which denotes the location of the current instruction being executed.
• is a group of electrical circuit, that performs the intent of instructions fetched from memory
• contains the address of the memory location that is to be read from or stored into
• contains a copy of the designated memory location specified by the MAR after a "read" or the new contents of the memory prior to a "write"

Question 212

More than one word are put in one cache block to

• exploit the temporal locality of reference in a program
• exploit the spatial locality of reference in a program
• reduce the miss penalty
• none of these

Question 213

The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used?

• 500 Kbytes/sec
• 2.2 Mbytes/sec
• 125 Kbytes/sec
• 250 Kbytes/sec

Question 214

In comparison with static RAM memory, the dynamic Ram memory has

• lower bit density and higher power consumption
• higher bit density and higher power consumption
• lower bit density and lower power consumption
• higher bit density and lower power consumption

Question 215

In the Big-Endian system, the computer stores

• MSB of data in the lowest memory address of data unit
• LSB of data in the lowest memory address of data unit
• MSB of data in the highest memory address of data unit
• LSB of data in the highest memory address of data uni

Question 216

How many PUSH and POP operations will be needed to evaluate the following expression by reverse polish notation in a stack machine (A ∗ B) + (C ∗ D / E)?

• 4 PUSH and 3 POP instructions
• 5 PUSH and 4 POP instructions
• 6 PUSH and 2 POP instructions
• 5 PUSH and 3 POP instructions

Question 217

A hierarchical memory system that uses cache memory has cache access time of 50 nano seconds, main memory access time of 300 nano seconds, 75% of memory requests are for read, hit ratio of 0.8 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?

• 157.5 n.sec.
• 110 n.sec.
• 75 n.sec.
• 82.5 n.sec.

Question 218

Temporal cohesion means

• Coincidental cohesion
• Cohesion between temporary variables
• Cohesion between local variables
• Cohesion with respect to time

Question 219

Various storage devices used by an operating system can be arranged as follows in increasing order of accessing speed:

• Magnetic tapes → magnetic disks → optical disks → electronic disks → main memory → cache → registers
• Magnetic tapes → magnetic disks → electronic disks → optical disks → main memory → cache → registers
• Magnetic tapes → electronic disks → magnetic disks → optical disks → main memory → cache → registers
• Magnetic tapes → optical disks → magnetic disks → electronic disks → main memory → cache → registers

Question 220

How many disk blocks are required to with 1 kB block size using linked list number is stored in 32 bits.

• 1024 blocks
• 16794 blocks
• 20000 blocks
• 1048576 blocks
• ALL are correct.