Combinational Circuits

Question 11

Given two three bit numbers a2a1a0 and b2b1b0 and c, the carry in, the function that represents the carry generate function when these two numbers are added is:

• A
• B
• C
• D

Question 12

We consider the addition of two 2’s complement numbers b_n-1b_n-2...b₀ and a_n-1a_n-2...a₀. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by c_n-1c_n-2...c₀ and the carry-out by c_out. Which one of the following options correctly identifies the overflow condition?

• A
• B
• C
• D

Question 13

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?

• 2

• 3

• 4

• 5

Question 14

Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f = T + R, without using any additional hardware ?

• R to X, 1 to Y, T to Z
• T to X, R to Y, T to Z
• T to X, R to Y, 0 to Z
• R to X, 0 to Y, T to Z

Question 15

A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

• 4 time units
• 6 time units
• 10 time units
• 12 time units

Question 16

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

• Θ(1)
• Θ(log n)
• Θ(n)
• Θ(n²)

Question 17

Consider the ALU shown below. If the operands are in 2\'s complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction respectively) ?

• A + B, and A - B, but not A + 1
• A + B, and A + 1, but not A - B
• A + B, but not A - B, or A + 1
• A + B, and A - B, and A + 1

Question 18

Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is "the output of the multiplexor. EN is the enable input. The function f(x, y, z) implemented by the above circuit is :

• xyz\'
• xy + z
• x + z
• None of these

Question 19

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using full adders. The total propagation time of this 4-bit binary adder in microseconds is

• 19.2 microseconds

• 16.4 microseconds

• 21.9 microseconds

• 17.6 microseconds

Question 20

The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?

• 1, 0, B
• 1, 0, A
• 0, 1, B
• 0, 1, A