UGC NET CS 2016 July – III Read Discuss Courses UGC NET CS 2016 July – III Please wait while the activity loads. If this activity does not load, try refreshing your browser. Also, this page requires javascript. Please visit using a browser with javascript enabled. If loading fails, click here to try again Question 1 Which of the following is a sequential circuit? Multiplexer Decoder Counter Full adder UGC NET CS 2016 July – III Digital Logic & Number representation Sequential circuits Discuss itQuestion 1-Explanation: Multiplexer, Decoder and Full adder are example of combinational circuits.Counter is a Sequential circuit. For more information on sequential circuits Refer:Digital Logic | Introduction of Sequential Circuits Option (C) is correct. Question 28085 microprocessor has _____ hardware interrupts.2345UGC NET CS 2016 July – III Microprocessor Discuss itQuestion 2-Explanation: 8085 microprocessor has 5 hardware interrupts. Named TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. 8086 microprocessor has 2 hardware interrupts. Named NMI and INTR. So, option (D) is correct.Question 3Which of the following in 8085 microprocessor performs HL = HL + DE ?DAD DDAD HDAD BDAD SPUGC NET CS 2016 July – III Discuss itQuestion 3-Explanation: DAD will perform Double addition (16 bit) between HL pair and any other pair of register. Among HL, BC, DE and SP; B, H and D register will be used first. So, DAD H will do HL = HL + HL; DAD B will do HL = HL + BC; DAD D will do HL = HL + DE; SP is stack pointer and it is not a pair register, DAD SP will do HL = HL + SP; So, option (A) is correct.Question 4The register that stores all interrupt requests is: Interrupt mask registerInterrupt service registerInterrupt request registerStatus registerUGC NET CS 2016 July – III Discuss itQuestion 4-Explanation: The register that stores all interrupt requests is Interrupt request register.Interrupt mask register is a read and write register. This register enables or masks interrupts from being triggered on the external pins of the Cache Controller.Interrupt service register handle the interrupt and service them according to priority and other condition.Status register is a hardware register that contains information about the state of the processor So, option (C) is correct.Question 5The _____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.Base indexedBase indexed plus displacementIndexedDisplacementUGC NET CS 2016 July – III Computer Organization and Architecture Pipelining and Addressing modes Discuss itQuestion 5-Explanation: The displacement addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX or BP and an index register SI or DI.Based Indexed plus displacement addressing mode: In this mode of addressing the operand’s offset is given by offset=[BX or BP]+[SI or DI]+8 bit or 16 bit displacement.Indexed addressing mode: The operand’s offset is the sum of the content of an index register SI or DI and an 8 bit or 16 bit displacement. So, option (D) is correct.Question 6In _____ method, the word is written to the block in both the cache and main memory, in parallel.Write throughWrite backWrite protectedDirect mappingUGC NET CS 2016 July – III Computer Organization and Architecture Pipelining and Addressing modes Discuss itQuestion 6-Explanation: In write through method, the word is written to the block in both the cache and main memory, in parallel and in write back method the word is written to the block in cache but actual update into the corresponding location in main memory only at specified intervals or under certain conditions. In Write Protected cache policy word cannot be modified or deleted. In direct mapping block M of main memory maps into block M modulo n of the cache, where n is the total number of blocks in cache. So, option (A) is correct.Question 7Which of the following statements concerning Object-Oriented databases is FALSE?Objects in an object-oriented database contain not only data but also methods for processing the data.Object-oriented databases store computational instructions in the same place as the data.Object-oriented databases are more adapt at handling structured (analytical) data than relational databases.Object-oriented databases store more types of data than relational databases and access that data faster.UGC NET CS 2016 July – III Discuss itQuestion 7-Explanation: Objects in an object-oriented database contain not only data but also methods for processing the data.CorrectObject-oriented databases store computational instructions in the same place as the data.CorrectObject-oriented databases are more adapt at handling structured (analytical) data than relational databases.IncorrectObject-oriented databases store more types of data than relational databases and access that data faster.CorrectSo, option (C) is correct.Question 8In distributed databases, location transparency allows for database users, programmers and administrators to treat the data as if it is at one location. A SQL query with location transparency needs to specify:InheritancesFragmentsLocationsLocal formatsUGC NET CS 2016 July – III SQL Discuss itQuestion 9Consider the relations R(A, B) and S(B, C) and the following four relational algebra queries over R and S: I. ΠA, B (R ⨝ S) II. R ⨝ ΠB(S) III. R ∩ (ΠA(R) × ΠB(S)) IV. ΠA, R.B (R × S) where R⋅B refers to the column B in table R. One can determine that:I, III and IV are the same query.II, III and IV are the same query.I, II and IV are the same query.I, II and III are the same query.UGC NET CS 2016 July – III Discuss itQuestion 10Which of the following statements is TRUE? D1 : The decomposition of the schema R(A, B, C) into R1(A, B) and R2 (A, C) is always lossless. D2 : The decomposition of the schema R(A, B, C, D, E) having AD → B, C → DE, B → AE and AE → C, into R1 (A, B, D) and R2 (A, C, D, E) is lossless.Both D1 and D2Neither D1 nor D2Only D1Only D2UGC NET CS 2016 July – III Database Design(Normal Forms) Discuss itQuestion 10-Explanation: Only D2 is True because AD is key and present in both the tables. D1 is not always true because FD’s not given and if we take B->A and C->A then it is lossy decomposition because no common attributes contain key from one of the table. 12345678 There are 75 questions to complete. You have completed questions question Your accuracy is Correct Wrong Partial-Credit You have not finished your quiz. If you leave this page, your progress will be lost. Correct Answer You Selected Not Attempted Final Score on Quiz Attempted Questions Correct Attempted Questions Wrong Questions Not Attempted Total Questions on Quiz Question Details Results Date Score Hint Time allowed minutes seconds Time used Answer Choice(s) Selected Question Text All doneNeed more practice!Keep trying!Not bad!Good work!Perfect! Last Updated : 06 Sep, 2021