Secondary memory and DMA



 
  
        
    
   
  

  
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Question 1
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. 

              Initialize the address register
              Initialize the count to 500
        LOOP: Load a byte from device
              Store in memory at address given by address register
              Increment the address register
              Decrement the count
              If count != 0 go to LOOP 


Assume that each statement in this program is equivalent to machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
A
3.4
B
4.4
C
5.1
D
6.7
GATE CS 2011    Computer Organization and Architecture    Secondary memory and DMA    
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Question 1 Explanation: 
 
 Explanation:
                        STATEMENT                                           CLOCK CYCLE(S) NEEDED
              Initialize the address register                                        1
              Initialize the count to 500                                            1
        LOOP: Load a byte from device                                                2
              Store in memory at address given by address register                   2
              Increment the address register                                         1
              Decrement the count                                                    1
              If count != 0 go to LOOP                                               1

        Interrrupt driven transfer time = 1+1+500×(2+2+1+1+1) = 3502
        DMA based transfer time = 20+500*2 = 1020
        Speedup = 3502/1020 ≈ 3.4

Source: http://clweb.csa.iisc.ernet.in/rahulsharma/gate2011key.html
Question 2
In a computer system, four files of size 11050 bytes, 4990 bytes, 5170 bytes and 12640 bytes need to be stored. For storing these files on disk, we can use either 100 byte disk blocks or 200 byte disk blocks (but can't mix block sizes). For each block used to store a file, 4 bytes of bookkeeping information also needs to be stored on the disk. Thus, the total space used to store a file is the sum of the space taken to store the file and the space taken to store the book keeping information for the blocks allocated for storing the file. A disk block can store either bookkeeping information for a file or data from a file, but not both.
What is the total space required for storing the files using 100 byte disk blocks and 200 byte disk blocks respectively?
A
35400 and 35800 bytes
B
35800 and 35400 bytes
C
35600 and 35400 bytes
D
35400 and 35600 bytes
Computer Organization and Architecture    Gate IT 2005    Secondary memory and DMA    
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Question 2 Explanation: 
 

Using 100 bytes disk blocks :


1. File of size 11050 bytes
Blocks required to store data = 11050/100 = 111
Blocks required for bookkeeping = (111 * 4)/100 = 5
Total blocks = 111 + 5 = 116


2. File of size 4990 bytes
Blocks required to store data = 4990/100 = 50
Blocks required for bookkeeping = (50 * 4)/100 = 2
Total blocks = 50 + 2 = 52


3. File of size 5170 bytes
Blocks required to store data = 5170/100 = 52
Blocks required for bookkeeping = (52 * 4)/100 = 3
Total blocks = 52 + 3 = 55


4. File of size 12640 bytes
Blocks required to store data = 12640/100 = 127
Blocks required for bookkeeping = (127 * 4)/100 = 6
Total blocks = 127 + 6 = 133


Total space required for storing the files using 100 byte disk blocks = (116 + 52 + 55 + 133) * 100 = 35600 bytes

 

Using 200 bytes disk blocks :


1. File of size 11050 bytes
Blocks required to store data = 11050/200 = 56
Blocks required for bookkeeping = (56 * 4)/200 = 2
Total blocks = 56 + 2 = 58


2. File of size 4990 bytes
Blocks required to store data = 4990/200 = 25
Blocks required for bookkeeping = (25 * 4)/200 = 1
Total blocks = 25 + 1 = 26


3. File of size 5170 bytes
Blocks required to store data = 5170/200 = 26
Blocks required for bookkeeping = (26 * 4)/200 = 1
Total blocks = 26 + 1 = 27


4. File of size 12640 bytes
Blocks required to store data = 12640/200 = 64
Blocks required for bookkeeping = (64 * 4)/200 = 2
Total blocks = 64 + 2 = 66


Total space required for storing the files using 100 byte disk blocks = (58 + 26 + 27 + 66) * 200 = 35400 bytes

 

Thus, option (C) is correct.

 

Please comment below if you find anything wrong in the above post.


Question 3
The size of the data count register of a DMA controller is 16 bits.  The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________

 
Note : This question was asked as Numerical Answer Type.
A
3644
B
3645
C
456
D
1823
Computer Organization and Architecture    GATE-CS-2016 (Set 1)    Secondary memory and DMA    
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Question 3 Explanation: 
 Size of data count register of the DMA controller = 16 bits
Data that can be transferred in one go = 216 bytes = 64 kilobytes
File size to be transferred = 29154 kilobytes
So, number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory = ceil(29154/64) = 456
 
Thus, C is the correct answer.
Question 4
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?

 
A
Transparent DMA and Polling interrupts
B
Cycle-stealing and Vectored interrupts
C
Block transfer and Vectored interrupts
D
Block transfer and Polling interrupts
OS Input Output Systems    Computer Organization and Architecture    GATE IT 2006    Secondary memory and DMA    
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Question 5
Which of the following systems is a most likely candidate example of a pipe and filter architecture ?
A
Expert system
B
DB repository
C
Aircraft flight controller
D
Signal processing
Computer Organization and Architecture    Gate IT 2007    Secondary memory and DMA    
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Question 5 Explanation: 
 Pipe and Filters

In the pipes and filters pattern, components are filters and connectors are pipes.
Each filter takes input insome form and produces output in some other form, 
which may or may not be similar to the input form.Hopefully,each filter will add 
value to the output stream because of processing done inside the filter. Each filter 
is independent and is unaware of the up and down stream filters. Pipes are conduits 
of the data streams. Famous example of the pipes and filters architectural pattern are
UNIX shells,signal processing systems and distributed systems.


Reference: Software Architecture: A Case Based Approach By Vasudeva Varma, Varma Vasudeva
Question 6
The main difference(s) between a CISC and a RISC processor is/are that a USC processor typically:
a) has fewer instructions
b) has fewer addressing modes
c) has more registers
d) is easier to implement using hardwired control logic
A
a and b
B
b and c
C
a and d
D
a, b, c and d
Computer Organization and Architecture    GATE CS 1999    Secondary memory and DMA    
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Question 7
The address space of 8086 CPU is
A
One Megabyte
B
256 Kilobytes
C
1 K Megabytes
D
64 Kilobytes
Computer Organization and Architecture    GATE CS 1998    Secondary memory and DMA    
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Question 8
If an instruction takes i microseconds and a page fault takes an additional j microseconds, the effective instruction time if on the average a  page fault occurs every k instructions is:
A
i + j/k
B
i  + j* k
C
(i + j)/ k
D
(i + j)* k
Computer Organization and Architecture    GATE CS 1998    Secondary memory and DMA    
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Question 9
The correct matching for the following pairs is

(A) DMA I/O                    (1) High speed RAM
(B) Cache                      (2) Disk
(C) Interrupt I/O              (3) Printer
(D) Condition Code Register    (4) ALU



Codes:
    A   B   C   D 
a   4   3   1   2
b   2   1   3   4
c   4   3   2   1
d   2   3   4   1

A
a
B
b
C
c
D
d
Computer Organization and Architecture    GATE CS 1997    Secondary memory and DMA    
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Question 10
For the daisy chain scheme of connecting I/O devices, which of the following statement is true?
A
It gives non-uniform priority to various devices
B
It gives uniform priority to all devices
C
It is only useful for connecting slow devices to a processor
D
It requires a separate interrupt pin on the processor for each device
Computer Organization and Architecture    GATE CS 1996    Secondary memory and DMA    
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