GATE CS 2022

Question 61

Consider an enterprise network with two Ethernet segments, a web server and a firewall, connected via three routers as shown below.

• 3

• 12

• 6

• 8

Question 62

Which of the following statements is/are TRUE?

• Every subset of a recursively enumerable language is recursive.

• If a language L and its complement L are both recursively enumerable, then L must be recursive.

• The complement of a context-free language must be recursive

• If L1 and L2 are regular, then L1∩ L2 must be deterministic context-free

Question 63

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is____________.

• 1.43

• 2.43

• 2.54

• 1.54

Question 64

Consider the queues Q1 containing four elements and Q2 containing none (shown as the Initial State in the figure). The only operations allowed on these two queues are Enqueue(Q, element) and Dequeue(Q). The minimum number of Enqueue operations on Q1 required to place the elements of Q1 in Q2 in reverse order (shown as the Final State in the figure) without using any additional storage is___________. 

• 12

• 9

• 4

• 0

Question 65

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

• Each cache block in WB and WT has a dirty bit

• Every write hit in WB leads to a data transfer from cache to main memory. 

• Eviction of a block from WT will not lead to data transfer from cache to main memory

• A read miss in WB will never lead to eviction of a dirty block from WB