Digital Logic & Number representation

Question 21

Consider the following Boolean function of four variables: f(w,x,y,z) = ∑(1,3,4,6,9,11,12,14) The function is:

• independent of one variables.
• independent of two variables.
• independent of three variables.
• dependent on all the variables.

Question 22

Let f(w, x, y, z) = ∑(0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are NOT equivalent to f?

• x\'y\'z\' + w\'xy\' + wy\'z + xz
• w\'y\'z\' + wx\'y\' + xz
• w\'y\'z\' + wx\'y\' + xyz + xy\'z
• x\'y\'z\' + wx\'y\' + w\'y

Question 23

Define the connective * for the Boolean variables X and Y as: X * Y = XY + X\' Y\'. Let Z = X * Y.

Consider the following expressions P, Q and R.
P: X = Y⋆Z 
Q: Y = X⋆Z 
R: X⋆Y⋆Z=1

Which of the following is TRUE?

• Only P and Q are valid
• Only Q and R are valid.
• Only P and R are valid.
• All P, Q, R are valid.

Question 24

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

• 2ⁿ line to 1 line
• 2ⁿ⁺¹ line to 1 line
• 2^n-1 line to 1 line
• 2^n-2 line to 1 line

Question 25

In a look-ahead carry generator, the carry generate function G_i and the carry propagate function P_i for inputs A_i and B_i are given by:

Pi = Ai ⨁ Bi and Gi = AiBi 

The expressions for the sum bit S_i and the carry bit C_i+1 of the look-ahead carry adder are given by:

Si = Pi ⨁ Ci and Ci+1 = Gi + PiCi , where C0 is the input carry. 

Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P_i and G_i are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively:

• 6, 3
• 10, 4
• 6, 4
• 10, 5

Question 26

The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”) The counter is connected as follows:
The counter is connected as follows: 
Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

• 0, 3, 4

• 0, 3, 4, 5

• 0, 1, 2, 3, 4

• 0, 1, 2, 3, 4, 5

Question 27

You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°? 

[caption width="800"] [/caption][caption width="800"] [/caption]

• A

• B

• C

• D

Question 28

Consider the following Boolean expression for F:

F(P, Q, R, S) = PQ + P\'QR + P\'QR\'S

The minimal sum-of-products form of F is

• PQ + QR + QS
• P + Q + R + S
• P\' + Q\' + R\' + S\'
• P\'R + P\'R\'S + P

Question 29

Consider a 4-to-1 multiplexer with two select lines S1 and S0, given below The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is

• P\'Q + QR\' + PQ\'R
• P\'Q + P\'QR\' + PQR\' + PQ\'R
• P\'QR + P\'QR\' + QR\' + PQ\'R
• PQR\'

Question 30

Let k = 2ⁿ. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2ⁿ bit decoder. This circuit is equivalent to a

• k-bit binary up counter.

• k-bit binary down counter.

• k-bit ring counter.

• k-bit Johnson counter.