Digital Logic & Number representation

Question 1
In the following truth table, V = 1 if and only if the input is valid. gatecs20133 What function does the truth table represent?
A
Priority encoder
B
Decoder
C
Multiplexer
D
Demultiplexer
GATE CS 2013    Digital Logic & Number representation    
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Question 1 Explanation: 
Since there are more than one outputs and number of outputs is less than inputs, it is a Priority encoder V=1 when input is valid and for priority encoder it checks first high bit encountered. Except all are having at least one bit high and ‘x’ represents the “don’t care” as we have found a high bit already. So answer is (A).
Question 2
Which one of the following expressions does NOT represent exclusive NOR of x and y?
A
xy+x'y'
B
x⊕y'
C
x'⊕y
D
x'⊕y'
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Question 2 Explanation: 
By Definition of XNOR, x\odot y = x' y' + xy So Option-A is correct. Also by Definition of XOR, x\oplus y = x' y + xy' Option-B is x\oplus y' = x' y' + x(y')' = x' y' + xy = x\odot y So Option-B is also correct. Option-C is x' \oplus y = (x')' y + x' y' = x' y' + xy = x\odot y Option-C is also correct. Option-D x'⊕y' = x''y' + x'y'' = xy' + x'y = x⊕y ≠ x⊙y Therefore option (D) is false. This explanation is provided by Chirag Manwani.
Question 3
The truth table truthtable represents the Boolean function
A
X
B
X+Y
C
X xor Y
D
Y
GATE CS 2012    Digital Logic & Number representation    
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Question 3 Explanation: 
The value of f(X, Y) is same as X for all input pairs. We see from truth table – Column x= f(x,y) So , f(x,y)=x Ans is (A) part.
Question 4
What is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t care term.
gatecs2012Kmap
A
b'd'
B
b'd' + b'c'
C
b'd' + a'b'c'd'
D
b'd' + b'c' + c'd'
Digital Logic & Number representation    
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Question 4 Explanation: 
There are two prime implicants in the following K-Map- Prime Implicant higlighted in Green = b'c' Prime Implicant higlighted in Orange = b'd' So the Boolean expression is- b'c' + b'd' Therefore option (B) is correct. This explanation is provided by Chirag Manwani.
Question 5
What is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t care term.
gatecs2012Kmap
A
b'd'
B
b'd' + b'c'
C
b'd' + a'b'c'd'
D
b'd' + b'c' + c'd'
Digital Logic & Number representation    
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Question 5 Explanation: 
There are two prime implicants in the following K-Map- Prime Implicant higlighted in Green = b'c' Prime Implicant higlighted in Orange = b'd' So the Boolean expression is- b'c' + b'd' Therefore option (B) is correct. This explanation is provided by Chirag Manwani.
Question 6
Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate? GATECS201113
A
A
B
B
C
C
D
D
GATE CS 2011    Digital Logic & Number representation    
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Question 6 Explanation: 
All options except D produce XOR as described below :  NOT({a \bigoplus b}) = XNOR \\ NOT(NOT(a)\bigoplus NOT(b)) = NOT(aNOT(b) + NOT(a)b) = XNOR \\ NOT(a) \bigoplus b = ab + NOT(ab)= XNOR \\ NOT(NOT(aNOT(b))(NOT(b)+a)) = NOT(NOT(ab)+ba) = NOT(XNOR)
Question 7
The simplified SOP (Sum Of Product) form of the boolean expression (P + Q' + R') . (P + Q' + R) . (P + Q + R') is
A
(P'.Q + R')
B
(P + Q'.R')
C
(P'.Q + R)
D
(P.Q + R)
GATE CS 2011    Digital Logic & Number representation    
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Question 7 Explanation: 
See following : (P+Q'+R').(P+Q'+R).(P+Q+R') = \prod(3, 2, 1) = \sum(0, 4, 5, 6, 7) gate2011A24 From the K-map, POS form is : P + Q'.R'
Question 8
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. GATECS2011Q50 If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
A
000
B
001
C
010
D
011
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Question 8 Explanation: 
P' = R Q' = (P + R)' R' = QR' Given that (P, Q, R) = (0, 1, 0), next state P', Q', R' = 0, 1, 1 ----------------------------------------------------------------------------------------------- D flip flop truth table
D Q(t+1)
0 0
1 1
Initially (p,q,r) =(0,1,0) D for p=R D for q=NOT(p xor r) D for r= (not)r.q So Q(t+1) for(p,q,r) p=>r=0 so p=0 q=> NOT(p xor r) => 1      so q=1 r=>(not)r.q => 1         so r=1 (p, q, r) = (0, 1, 1) Alternative approach - Truth table of a D Flip-Flop-  \begin{tabular}{|c|c|} \hline D_{t} & Q_{t+1}\\ \hline 0 & 0\\ \hline 1 & 1\\ \hline \end{tabular} By looking at the circuit diagram, it is clear that the boolean expressions of P, Q, and R are- Here the subscript t refers to the current clock cycle, and the subscript (t+1) refers to the next clock cycle. Q_{P(t+1)} = P_{t+1} = R_t Q_{Q(t+1)} = Q_{t+1} = R_{t}' P_{t}' Q_{R(t+1)} = R_{t+1} = Q_{t} R_{t}'  \begin{tabular}{|c|c|c|} \hline D_{t} & Q_{t+1}\\ \hline 0 & 0\\ \hline 1 & 1\\ \hline \end{tabular} This explanation is provided by Chirag Manwani.
Question 9
Consider the data given in previous question. If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter?
A
3
B
4
C
5
D
6
GATE CS 2011    Digital Logic & Number representation    
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Question 9 Explanation: 
There are four distinct states, 000 → 010 → 011 → 100 (→ 000) so the answer is B
Question 10
The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is
A
m2 + m4 + m6 + m7
B
m0 + m1 + m3 + m5
C
m0 + m1 + m6 + m7
D
m2 + m3 + m4 + m5
GATE CS 2010    Digital Logic & Number representation    
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Question 10 Explanation: 
CSE_2010_06_ans
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