Pipelining and Addressing modes

Question 91

More than one word are put in one cache block to

• exploit the temporal locality of reference in a program
• exploit the spatial locality of reference in a program
• reduce the miss penalty
• none of these

Question 92

A particular parallel program computation requires 100 sec when executed on a single processor. If 40% of this computation is inherently sequential (i.e. will not benefit from additional processors), then theoretically best possible elapsed times of this program running with 2 and 4 processors, respectively, are

• 20 sec and 10 sec
• 30 sec and 15 sec
• 50 sec and 25 sec
• 70 sec and 55 sec

Question 93

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5- stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is __________ . Note - This question was Numerical Type.

• 2.16
• 2.50
• 1.50
• 1.16

Question 94

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______ . Note - This question was Numerical Type.

• 14
• 15
• 16
• 12