GATE-CS-2017 (Set 1)

Question 41

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC- relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence 

If the target of the branch instruction is i, then the decimal value of the Offset is __________. 

Note: This questions appeared as Numerical Answer Type.

• -16

• -18

• 16

• 18

Question 42

Consider the following grammar over the alphabet {a,b,c} given below, S and T are non-terminals.

G1: S-->aSb|T
T--> cT|∈

G2: S-->bSa|T
T--> cT|∈

The language L1(G1) ∩ L2(G2).

• Finite
• Non-finite but regular
• Context-free but not regular
• Recursive but not context-free

Question 43

If G is grammar with productions

S → SaS | aSb | bSa | SS | ∈

where S is the start variable, then which one of the following is not generated by G?

• abab
• aaab
• abbaa
• babba

Question 44

In a RSA cryptosystem a particular A uses two prime numbers p = 13 and q =17 to generate her public and private keys. If the public key of Ais 35. Then the private key of A is ____________.

Note: This questions appeared as Numerical Answer Type.

• 11
• 13
• 16
• 17

Question 45

Let A be m×n real valued square symmetric matrix of rank 2 with expression given below.

Consider the following statements 

(i)  One eigenvalue must be in [-5, 5].
(ii) The eigenvalue with the largest magnitude 
     must be strictly greater than 5.

Which of the above statements about eigenvalues of A is/are necessarily CORRECT?

• Both (i) and (ii)

• (i) only

• (ii) only

• Neither (i) nor (ii)

Question 46

In a database system, unique time stamps are assigned to each transaction using Lamport’s logical clock. Let TS(T1) and TS(T2) be the time stamps of transactions T1 and T2 respectively. Besides, T1 holds a lock on the resource R, and T2 has requested a conflicting lock on the same resource R. The following algorithm is used to prevent deadlocks in the database assuming that a killed transaction is restarted with the same timestamp.

if  TS(T2) <TS(T1) then
      T1 is killed
else T2  waits.

Assume any transactions that is not killed terminates eventually. Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks?

• The database system is both deadlock-free and starvation- free.
• The database system is deadlock- free, but not starvation-free.
• The database system is starvation-free but not deadlock- free.
• The database system is neither deadlock- free nor starvation-free.

Question 47

The values of parameters for the Stop-and – Wait ARQ protocol are as given below.

Bit rate of the transmission channel = 1Mbps

Propagation delay from sender to receiver = 0.75 ms
 
Time to process a frame = 0.25ms
 
Number of bytes in the information frame = 1980
   
Number of bytes in the acknowledge frame = 20
 
Number of overhead bytes in the information frame = 20 

Assume that there are no transmission errors. Then the transmission efficiency ( expressed in percentage) of the Stop-and – Wait ARQ protocol for the above parameters is _________( correct to 2 decimal place) .

Note: This questions appeared as Numerical Answer Type.

• A number between 86.5 and 87.5
• A number between 82.4 and 82.5
• A number between 92.4 and 95.5
• A number between 96.4 and 97.5

Question 48

The value of the given expression

• 0
• -1
• 1
• Does not exist

Question 49

Consider the following two functions

void fun1(int n){ 

     if(n == 0) return; 
     printf(“%d”, n); 
     fun2(n-2);
     printf(“%d”, n);  
}

void fun2(int n){ 

     if(n == 0) return; 
     printf(“%d”, n); 
     fun1(++n);
     printf(“%d”, n);  
}

The output printed when fun1 (5) is called is

• 53423122233445
• 53423120112233
• 53423122132435
• 53423120213243

Question 50

Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is empty. Conflict misses are those misses which occur due the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks

(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129) 

is repeated 10 times. The number of conflict misses experienced by the cache is ___________.

Note: This questions appeared as Numerical Answer Type.

• 78
• 76
• 74
• 80