GATE-CS-2001

Question 31

Consider the following languages [Tex]L1=\\left \\{ ww|w\\in \\left \\{ a,b \\right \\}*\\right \\}[/Tex] [Tex]L2=\\left \\{ ww^{R}|w\\in \\left \\{ a,b \\right \\}*, w^{R} is\\ the\\ reverse\\ of\\right\\ w \\}[/Tex] [Tex]L3=\\left \\{ 0^{2i}| i\\ is\\ an\\ integer \\}[/Tex] [Tex]L4=\\left \\{ 0^{i^{2}}| i\\ is\\ an\\ integer \\}[/Tex] Which of the languages are regular?

• Only L1 and L2

• Only L2, L3 and L4

• Only L3 and L4

• Only L3

Question 32

Consider the following problem X.

Given a Turing machine M over the input alphabet Σ, any
state q of M And a word w∈Σ*, does the computation of M
on w visit the state q? 

Which of the following statements about X is correct?

• X is decidable
• X is undecidable but partially decidable
• X is undecidable and not even partially decidable
• X is not a decision problem

Question 33

Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0. Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?

• a

• b

• c

• d

Question 34

Which is the most appropriate match for the items in the first column with the items in the second column

X. Indirect Addressing        I. Array implementation
Y. Indexed Addressing         II. Writing re-locatable code
Z. Base Register Addressing   III. Passing array as parameter

• (X, III) (Y, I) (Z, II)
• (X, II) (Y, III) (Z, I)
• (X, III) (Y, II) (Z, I)
• (X, I) (Y, III) (Z, II)

Question 35

The 2’s complement representation of (−539)₁₀ in hexadecimal is

• ABE
• DBC
• DE5
• 9E7

Question 36

Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac\' + bc).

Which of the following is true?

• f = x1\'+ x1x
• f = x1\'x2 + x1x2\'
• f = x1x2 + x1\'x2\'
• f = x1 + x2\'

Question 37

Consider the circuit given below with initial state Q0 =1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the correct state sequence of the circuit?

• 1,3,4,6,7,5,2

• 1,2,5,3,7,6,4

• 1,2,7,3,5,6,4

• 1,6,5,7,2,3,4

Question 38

Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where = A or B, has the specification
M [SP] ← r
SP ← SP – 1
How many CPU clock cycles are needed to execute the “push r” instruction?

• 1

• 3

• 4

• 5

Question 39

Consider the following graph:

[caption width="800"]Graph[/caption]

Which edges would be included in the minimum spanning tree using Prim's algorithm starting from vertex A?

Options: a)  b)  c)  d) 

• AB, BD, DE, EF, FC

• AC, CD, DE, EB, BF

• AB, BD, DE, EC, CF

• AC, CD, DE, EB, FE

Question 40

How many undirected graphs (not necessarily connected) can be constructed out of a given set V = {v1, v2, ... vn} of n vertices?

• n(n-1)/2
• 2ⁿ
• n!
• 2^n(n-1)/2