In 8085 microprocessor which of the following flag(s) is (are) affected by an arithmetic operation ?
AC flag Only
CY flag Only
Z flag Only
AC, CY, Z flags
Question 1 Explanation:
AC is auxiliary-Carry flag, CY is Carry flag and Z is Zero flag. All these flags will be affected during arithmetic operation. So, option (D) is correct.
In 8085 microprocessor the address bus is of __________ bits.
Question 2 Explanation:
In 8085 microprocessor 16 bits are used for address bus and 65,536(216 = 65,536) different memory location are possible. So, option (C) is correct.
In the architecture of 8085 microprocessor match the following:
Question 3 Explanation:
- ALU is the arithmetic logic unit and it involves processing of input into desired output.
- Timing and control instruction are covered in instruction unit of microprocessor.
- There are some general purpose register in storage and interface unit.
- While an interrupt is a signal to the processor which required attention from processor, an interrupt is serviced on the basis of priorty and need.
Which of the following addressing mode is best suited to access elements of an array of contiguous memory locations ?
Indexed addressing mode
Base Register addressing mode
Relative address mode
Question 4 Explanation:
Indexed addressing mode is best suited for accessing an array in contiguous memory location. For detailed information on addressing modes Refer:Addressing_Modes. So, option (A) is correct.
Which of the following is correct statement ?
In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words.
The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.
In asynchronous serial transfer of data the two units share a common clock.
In synchronous serial transmission of data the two units have different clocks.
Question 5 Explanation:
- The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.
- Memory based I/O uses same address space for memory and I/O devices.
- In asynchronous serial transfer of data the two units do not share a common clock.
- In synchronous serial transfer of data the two units share a common clock.
A micro-instruction format has micro-ops field which is divided into three subfields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations. The size of micro-instruction is:
Question 6 Explanation:
Microprocessor instruction format, which is divided into three subfields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations.ie: F1,F2,F3 each having seven distinct micro-operation. So, 3 bits are required for each. Condition field have four status, it needs 2 bits for four different condition. Branch field have four option so,it needs 2 bits for four option. Now there are 128 different memory location, So, there 7 bits atre required for 128 diffeent location. Instruction Field: Total bits are 20. So, option (B) is correct.
Consider the following four schedules due to three transactions (indicated by the subscript) using read and write on a data item X, denoted by r(X) and w(X) respectively. Which one of them is conflict serializable ?
S1: r1(X); r2(X); w1(X); r3(X); w2(X) S2: r2(X); r1(X); w2(X); r3(X); w1(X) S3: r3(X); r2(X); r1(X); w2(X); w1(X) S4: r2(X); w2(X); r3(X); r1(X); w1(X)
Question 7 Explanation:
We can draw precedence graph for each schedule and for conflict serializability graph must not contain cycle. Refer:Gate_CS 2014 So, option (D) is correct.
Suppose a database schedule S involves transactions T1, T2, .............,Tn. Consider the precedence graph of S with vertices representing the transactions and edges representing the conflicts. If S is serializable, which one of the following orderings of the vertices of the precedence graph is guaranteed to yield a serial schedule ?
Depth - first order
Breadth - first order
Ascending order of transaction indices
Question 8 Explanation:
For a schedule, we can check its serializability by drawing a precedence graph and find its topological order, precedence graph of schedule must not contain any cycle to be conflict free. Refer:GATE-CS-2016 So, option (A) is correct.
If every non-key attribute is functionally dependent on the primary key, then the relation is in __________ .
First normal form
Second normal form
Third normal form
Fourth normal form
Question 9 Explanation:
Conditions for various normal forms:
- 1 NF - A relation R is in first normal form (1NF) if and only if all underlying domains contain atomic values only.
- 2 NF - A relation R is in second normal form (2NF) if and only if it is in 1NF and every non-key attribute is fully dependent on the primary key.
- 3 NF - A relation R is in third normal form (3NF) if and only if it is in 2NF and every non-key attribute is non-transitively dependent on the primary key.
- BCNF - A relation R is in Boyce-Codd normal form (BCNF) if and only if every determinant is a candidate key.
Consider a relation R (A, B, C, D, E, F, G, H), where each attribute is atomic, and following functional dependencies exist.
CH → G A → BC B → CFH E → A F → EGThe relation R is __________ .
in 1NF but not in 2NF
in 2NF but not in 3NF
in 3NF but not in BCNF
Question 10 Explanation:
If we find closure of A: A+ → All atribute except D. Similarly for other keys we can find closure, but D can't be derived from any key and it must be added to all keys to be derived from. That's why this relation is in 1NF, since there is partial dependency so, this relation is not in 2NF. So, option (A) is correct.
There are 75 questions to complete.
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