Digital Logic & Number representation

Question 1
In the following truth table, V = 1 if and only if the input is valid. gatecs20133 What function does the truth table represent?
A
Priority encoder
B
Decoder
C
Multiplexer
D
Demultiplexer
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Question 1 Explanation: 
Since there are more than one outputs and number of outputs is less than inputs, it is a Priority encoder V=1 when input is valid and for priority encoder it checks first high bit encountered. Except all are having at least one bit high and ‘x’ represents the “don’t care” as we have found a high bit already. So answer is (A).
Question 2
Which one of the following expressions does NOT represent exclusive NOR of x and y?
A
xy + x' y'
B
x ^ y' where ^ is XOR
C
x' ^ y where ^ is XOR
D
x' ^ y' where ^ is XOR
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Question 2 Explanation: 
It is a simple De Morgan's laws question.  
Question 3
The truth table truthtable represents the Boolean function
A
X
B
X+Y
C
X xor Y
D
Y
GATE CS 2012    Digital Logic & Number representation    
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Question 3 Explanation: 
The value of f(X, Y) is same as X for all input pairs. We see from truth table – Column x= f(x,y) So , f(x,y)=x Ans is (A) part.
Question 4
W hat is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t care term.
gatecs2012Kmap
A
b'd'
B
b'd' + b'c'
C
b'd' + a'b'c'd'
D
b'd' + b'c' + c'd'
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Question 4 Explanation: 
gatecs2012KmapSolution
Question 5
Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate? GATECS201113
A
A
B
B
C
C
D
D
GATE CS 2011    Digital Logic & Number representation    
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Question 5 Explanation: 
All options except D produce XOR. See following image (Source: http://clweb.csa.iisc.ernet.in/rahulsharma/gate2011key.html) gate201113
Question 6
The simplified SOP (Sum Of Product) form of the boolean expression (P + Q' + R') . (P + Q' + R) . (P + Q + R') is
A
(P'.Q + R')
B
(P + Q'.R')
C
(P'.Q + R)
D
(P.Q + R)
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Question 6 Explanation: 
Question 7
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. GATECS2011Q50 If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
A
000
B
001
C
010
D
011
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Question 7 Explanation: 
P' = R Q' = (P + R)' R' = QR' Given that (P, Q, R) = (0, 1, 0), next state P', Q', R' = 0, 1, 1 ----------------------------------------------------------------------------------------------- D flip flop truth table
D Q(t+1)
0 0
1 1
Initially (p,q,r) =(0,1,0) D for p=R D for q=NOT(p xor r) D for r= (not)r.q So Q(t+1) for(p,q,r) p=>r=0 so p=0 q=> NOT(p xor r) => 1      so q=1 r=>(not)r.q => 1         so r=1 (p,q,r)=(0,1,1)
Question 8
Consider the data given in previous question. If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter?
A
3
B
4
C
5
D
6
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Question 8 Explanation: 
There are four distinct states, 000 → 010 → 011 → 100 (→ 000) so the answer is B
Question 9
The minterm expansion of f(P, Q, R) = PQ + QR' + PR' is
A
m2 + m4 + m6 + m7
B
m0 + m1 + m3 + m5
C
m0 + m1 + m6 + m7
D
m2 + m3 + m4 + m5
GATE CS 2010    Digital Logic & Number representation    
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Question 9 Explanation: 
CSE_2010_06_ans
Question 10
The Boolean expression for the output 'f' of the multiplexer shown below is CSE_201009
A
(P(XOR)Q(XOR)R)'
B
P(XOR)Q(XOR)R
C
(P+Q+R)'
D
P+Q+R
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Question 10 Explanation: 
For 4 to 1 mux truth table SEL                  INPUT                 O/P
Q P R R’ R’ R F
0 0 X X X 1 1
0 1 X X 1 X 1
1 0 X 1 X X 1
1 1 1 X X X 1
p’q’r+p’qr’+pq’r’+pqr pXORqXORr
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