Digital Logic || 2014 MCQ || 2-mark || Module 4: Sequential Circuit

Last Updated :
Discuss
Comments


unnamed-9
img

The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1Q0=000. The state sequence for this circuit for the next 3 clock cycles is: [GATE||2014||SET3||MCQ||2MARKS]


001, 010, 011

111, 110, 101

100, 110, 111

100, 011, 001

This question is part of this quiz :

GATE|| Digital logic || Pyq (2010 to 2025),GATE || DIGITAL ELECTRONICS / LOGIC ||PYQ (2010 TO2025),GATE || DIGITAL LOGIC || SEQUENTIAL CIRCUIT || PYQ (2010 TO 2025 )
Tags:
GATE CS
GATE
Digital Logic
SEQUENTIAL CIRCUIT
Share your thoughts in the comments
Article Tags :