Digital Logic || 2017 MCQ || 2-mark || Module 4: Sequential Circuit

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Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.

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Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs [GATE 2017|| SET1 || MCQ||2 Marks]


Q1Q0 after 3rd cycle are 11 and after the 4th cycle are 00 respectively

Q1Q0 after 3rd cycle are 11 and after the 4th cycle are 01 respectively

Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 11 respectively

Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively

This question is part of this quiz :

GATE|| Digital logic || Pyq (2010 to 2025),GATE || DIGITAL ELECTRONICS / LOGIC ||PYQ (2010 TO2025),GATE || DIGITAL LOGIC || SEQUENTIAL CIRCUIT || PYQ (2010 TO 2025 )
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GATE CS
GATE
Digital Logic
SEQUENTIAL CIRCUIT
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