Digital Logic || 2017 MCQ ||1-mark || Module 3: Combinational Circuit

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When two 8-bit numbers A7...A0 and B7...B0 in 2’s complement representation (with A0 and B0 as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are S7...S0 and the carry bits are C7...C0. An overflow is said to have occurred if [GATE||2017||SET1||MCQ||1MARKS]



the carry bit C7 is 1

all the carry bits (C7,…,C0) are 1

(A7 . B7 . S7' + A7' . B7' . S7) is 1

(A0 . B0 . S0' + A0' . B0' . S0) is 1

This question is part of this quiz :

GATE || DIGITAL ELECTRONICS / LOGIC ||PYQ (2010 TO2025),GATE || DIGITAL LOGIC || COMBINATIONAL CIRCUIT || PYQ (2010 TO 2025 )
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Digital Logic
Combinational Circuit
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