COA-2014-PYQs-MCQ-2-mark- MODULE. 6COA

An instruction pipeline has five stages, namely:

1. Instruction Fetch (IF) – latency = 1 ns
2. Instruction Decode and Register Fetch (ID/RF) – latency = 2.2 ns
3. Instruction Execution (EX) – latency = 2 ns
4. Memory Access (MEM) – latency = 1 ns
5. Register Write Back (WB) – latency = 0.75 ns

(ns stands for nanoseconds).

To gain in terms of frequency, the designers have decided to:

• Split the ID/RF stage into three stages (ID, RF1, RF2) each of latency:

2.2/3 ns ≈ 0.73ns

• Split the EX stage into two stages (EX1, EX2) each of latency 1 ns.

Thus, the new design has a total of 8 pipeline stages.

A program has 20% branch instructions, which execute in the EX stage and produce the next instruction pointer:

• At the end of the EX stage in the old design.
• At the end of the EX2 stage in the new design.

The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed.

• All instructions other than branch instructions have an average CPI = 1 in both designs.
• The execution times of this program on the old and the new design are P and Q nanoseconds, respectively.

The value of  Q/P​ = ?
[GATE 2014 || SET-3 MCQ || 2 marks]