COA-2014-PYQs-MCQ-2-mark- MODULE.7COA

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If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
[GATE 2014|| SET-2 MCQ || 2 marks]


Width of tag comparator

Width of set index decoder

Width of way selection multiplexor


Width of processor to main memory data bus

This question is part of this quiz :

GATE||COA|| Pipelining and Secondary Memory || Pyqs (2010 to 2025 ),GATE||COA|| Pyqs (2010 to 2025 )
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