In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are replaced in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from
[GATE 2013|| MCQ || 1 marks]
(j mod v) * k to (j mod v) * k + (k – 1)
(j mod v) to (j mod v) + (k – 1)
(j mod k) to (j mod k) + (v – 1)
(j mod k) * v to (j mod k) * v + (v – 1)
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GATE||COA|| Pipelining and Secondary Memory || Pyqs (2010 to 2025 ),GATE||COA|| Pyqs (2010 to 2025 )