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Microprocessor

Question 1
Which of the following addressing modes are suitable for program relocation at run time ?
(i)   Absolute addressing
(ii)  Based addressing
(iii) Relative addressing
(iv)  Indirect addressing
A
(i) and (iv)
B
(i) and (ii)
C
(ii) and (iii)
D
(i), (ii) and (iv)
GATE-CS-2004    Microprocessor    
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Question 1 Explanation: 
Explanation: Program relocation at run time transfer complete block to some memory locations. This requires as base address and block should be relatively addressed through this base address .This require both base address and relative address. So( C)  is correct option. Absolute addressing mode and indirect addressing modes is used for one instruction at one time, not for whole block So both are not suitable for program relocation at run time.
Question 2
Directions for question 63 to 64: Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.
 Instruction 	 Operation 	 Instruction Size(in words)
 MOV R1,5000; 	 R1 ¬ Memory[5000] 	 2
 MOV R2, (R1); 	 R2 ¬ Memory[(R1)] 	 1
 ADD R2, R3; 	 R2 ¬ R2 + R3 	         1
 MOV 6000, R2; 	 Memory [6000] ¬ R2 	 2
 HALT 	         Machine halts 	         1 
Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be
A
1007
B
1020
C
1024
D
1028
GATE-CS-2004    Microprocessor    
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Question 2 Explanation: 
Instruction size are given in words. So first instruction will take 2 words i.e 8 bytes(as 32 bit byte addressable, word size will be 32 bit ) so on for 2nd instruction 4 byte, for 3rd 4 bytes, 4th 8 bytes..5th 4 bytes. As 1st instruction starts from 1000 and the size is 8 bytes second instruction address will be 1008, like wise 3rd instruction address will be 1012,4th instruction address 1016,5th instruction address 1024 and halt instruction address will be 1028. As an interrupt occurs executing the HALT instruction, the return address (in decimal) saved in the stack will be the address of the halt instruction ..so answer is 1028.
Question 3
Directions for question 63 to 64: Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.
 Instruction 	 Operation 	 Instruction Size(in words)
 MOV R1,5000; 	 R1 ¬ Memory[5000] 	 2
 MOV R2, (R1); 	 R2 ¬ Memory[(R1)] 	 1
 ADD R2, R3; 	 R2 ¬ R2 + R3 	         1
 MOV 6000, R2; 	 Memory [6000] ¬ R2 	 2
 HALT 	         Machine halts 	         1
Let the clock cycles required for various operations be as follows: Register to/ from memory transfer: 3 clock cycles ADD with both operands in register : 1 clock cycle Instruction fetch and decode : 2 clock cycles per word The total number of clock cycles required to execute the program is
A
29
B
24
C
23
D
20
GATE-CS-2004    Microprocessor    
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Question 3 Explanation: 
The clock cycles are per block; if an instruction size is 2 then it requires twice no. of clock cycles.
Instruction no.       size                                              no. of clock cycles
1                                2                                                                       3*2+2
2                                1                                                                       1*3+2
3                                1(add only)                                                      1
4                                2                                                                       3*2+2
5                                1                                                                       2(fetch and decode)
                                Total                                                                  24
  So answer is (B)
Question 4
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. GATECS2004Q65 How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?
A
10, 3, 1024
B
8, 5, 256
C
5, 8, 2048
D
10, 3, 512
GATE-CS-2004    Microprocessor    
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Question 4 Explanation: 
MUX has 8 states bits as input lines so we require 3 select inputs to select and input lines. No. of bits in control memory next address field=26-13-3 =10 10 bit addressing .we have 2 10 memory size So X,Y size=10,3 So (A) is correct option.
Question 5
Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.
 MOV B, # 0 ;    B ← 0
 MOV C, # 8 ;    C ← 8
Z :  CMP C, # 0 ;    compare C with 0
 JZX ;    jump to X if zero flag is set
 SUB C, # 1 ;    C ← C - 1
 RRC A, # 1 ;    right rotate A through carry by one bit. Thus:
;    if the initial values of A and the carry flag are a7...a0 and
;    c0 respectively, their values after the execution of this
;    instruction will be c0a7...a1 and a0 respectively.
 JC Y ;    jump to Y if carry flag is set
 JMP Z ;    jump to Z
Y :  ADD B, # 1 ;    B ← B + 1
 JMP Z ;    jump to Z
X :
A
the number of 0 bits in A0
B
the number of 1 bits in A0
C
A0
D
8
Microprocessor    GATE-CS-2003    
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Question 5 Explanation: 
Answer: (B) Explanation: Explanation: Here value of B incremented by 1 only if carry flag is 1 and carry is filled always using right rotation. So B will store the no. of 1s in A0. RRC instruction is(  Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. Any other bit is not affected). So A=A0, and after execution RRC A,#1, carry flag is set,it goes to Y,which is B=B+1,Which becomes B=0+1=1   So (B) is correct option
Question 6
Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.
MOV B, # 0 ; B ← 0
MOV C, # 8 ; C ← 8
Z : CMP C, # 0 ; compare C with 0
JZX ; jump to X if zero flag is set
SUB C, # 1 ; C ← C - 1
RRC A, # 1 ; right rotate A through carry by one bit. Thus:
; if the initial values of A and the carry flag are a7...a0 and
; c0 respectively, their values after the execution of this
; instruction will be c0a7...a1 and a0 respectively.
JC Y ; jump to Y if carry flag is set
JMP Z ; jump to Z
Y : ADD B, # 1 ; B ← B + 1
JMP Z ; jump to Z
X :
Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its initial value ?
A
RRC A, #
B
NOP ; no operation
C
LRC A, # 1 ; left rotate A through carry flag by one bit
D
ADD A, # 1
Microprocessor    GATE-CS-2003    
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Question 6 Explanation: 
Explanation In the end of program execution to check whether both initial and final value of register A is A0,we need to right rotate register A through carry by one bit because RRC instruction is( Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. Any other bit is not affected). So (A) is correct option
Question 7
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
		 
A)      gatecs2002Q8 is active
B)	HOLD is active
C)	READY is active
D)	None of these
A
A
B
B
C
C
D
D
Microprocessor    GATE-CS-2002    
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Question 7 Explanation: 
Explanation: INTR is a signal which if enabled then microprocessor has interrupt enabled .It receives high INTR signal and activates INTA signal, So another request can’t be accepted till CPU is busy in servicing interrupt So (A) is correct option.
Question 8
In 8085, which of the following modifies the program counter ?
A
Only PCHL instruction
B
Only ADD instructions
C
Only JMP and CALL instructions
D
All instructions
Microprocessor    GATE-CS-2002    
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Question 8 Explanation: 
Program counter is the register which has the next location of the program to be executed next. JMP & CALL changes the value of PC. PCHL instruction copies content of registers H & L to PC. ADD instruction after completion increments program counter. So program counter is modified in all cases. Hence (D) is correct option.
Question 9
In the absolute addressing mode
A
the operand is inside the instruction
B
the address of the operand is inside the instruction
C
the register containing address of the operand is specified inside the instruction
D
the location of the operand is implicit
Microprocessor    GATE-CS-2002    
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Question 9 Explanation: 
(b) is the answer. Absolute addressing mode means address of operand is given in the instruction. (a) operand is inside the instruction -> immediate addressing (c) -> register addressing (d) -> implicit addressing
Question 10
What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program?
   MVI L, 5DH
   MVI L, 6BH
   MOV A, H
   ADD L
A
AC = 0 and CY = 0
B
AC = 1 and CY = 1
C
AC = 1 and CY = 0
D
AC = 0 and CY = 0
Microprocessor    GATE-CS-2002    
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Question 10 Explanation: 
  First we load  5D in L register But we have not stored it to the accumulator So, when we load 6B in L register, it overwrites 5D in L register and the same value 6BH is copied to accumulator Now A = 6BH L = 6BH ADD L i.e. A = A + L It will generate internal carry i.e. B + B = 22 i.e. 22 - 16 = 6 adding 2 to 6 + 6 => we get 14 => D Hence answer is D6 Since there is internal carry only, no final carry as 14 < 16 So, Auxillary carry flag(AC) = 1 Carry Flag(CY) = 0       This solution is contributed by Mohit Gupta .
There are 19 questions to complete.
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