PCIe stands for Peripheral Component Interconnect express. It is an interface standard that is used to connect high-speed components. PCIe is available in a different physical configuration which includes x1, x4, x8, x16, x32. The motherboard has a number of PCIe slots to connect different components such as GPU(or video cards or graphics cards ), WI-FI cards, SSD (Solid-state drive). Different motherboards have different types of PCIe slots.
Generation of PCIe
Till now six generations of PCIe have been introduced in the market i.e PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0, PCIe 6.0 out of these only first four have been debuted in the market. PCIe 4.0 was first introduced in 2019 by AMD Ryzen 3000-series CPUs.
Arapaho Work Group (AWG), initially consisted of Intel engineers, later expanded to include industry partners, draw this standard. First PCIe as named as High-Speed Interconnect (HSI), then renamed to 3GIO (3rd generation I/O) and finally renamed to PCIe.
- PCIe 1.0a: It was introduced by PCI-SIG in year 2003. It has a per-lane data rate of 250 MB/s and a transfer rate of 2.5 Giga transfers per second (GT/s).
- PCIe 1.1: It was introduced by PCI-SIG in year 2005. It has more clarification and improvement over PCIe 1.0a but per-lane data rate and transfer rate was unchanged.
- PCIe 2.0: It was introduced by PCI-SIG in year 2007. It doubled the per-lane data rate and transfer rate compared to PCIe 1.0. It has a per-lane data rate of 500MB/s instead of 250 MB/s and a transfer rate of 5GT/s instead of 2.5 Giga transfers per second (GT/s). PCIe 2.0 slots provides backward compatibility with PCIe 1.x cards.
- PCIe 3.0: It was introduced by PCI-SIG in November 2010, after multiple delays. In August 2007, PCI-SIG announced backward compatible with existing PCI Express implementations and a bit rate of 8 Giga transfers per second (GT/s) for PCI Express 3.0. PCI-SIG also announced, a delay in release until Q2 2010 for the final specification for PCI Express 3.0. A number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies were added in PCI Express 3.0 specification
It has a per-lane data rate of 984.6MB/s instead of 500MB/s (as in PCIe 2.0) and a transfer rate of 8GT/s instead of 5 GT/s (as in PCIe 2.0).
- PCIe 4.0: It was introduced by PCI-SIG on November 29, 2011. It doubled the per-lane data rate and transfer rate compared to PCIe 3.0. It has a per-lane data rate of 1969MB/s instead of 984.6MB/s (as in PCIe 3.0) and a transfer rate of 16GT/s instead of 8 GT/s (as in PCIe 3.0). PCIe 4.0 provides full backward and forward compatibility.
- PCIe 5.0: PCI Express 5.0 preliminary specification was introduces by PCI-SIG in JUNE, 2017. In a 16-lane configuration Bandwidth was expected to increase to 32 GT/s, yielding 63 GB/s in each direction. The draft was expected to be standardized in 2019. Final PCI-Express 5.0 specification was introduced by PCI-SIG On 29 May 2019. The mass production for PCIe 5.0 is planned to start in 2020.
- PCIe 6.0: PCI-SIG announced the development of PCI Express 6.0 specification On June 18, 2019. In a 16-lane configuration bandwidth is expected to increase to 64 GT/s, yielding 128 GB/s in each direction. It has a target release date of 2021. 4-level pulse-amplitude modulation (PAM-4) with low-latency forward error correction (FEC) in place of non-return-to-zero (NRZ) modulation is used in this new standard. Forward error correction is used to increase data integrity and PAM-4 is used as line code so that two bits are transferred per transfer which was not provided in the earlier version. It has 64 GT/s data transfer rate (raw bit rate) and up to 256 GB/s via x16 configuration.
|PCIe 1.0||8 GB/s||2.5 GT/s||2.5 GHz||8b/10b|
|PCIe 2.0||16 GB/s||5 GT/s||5.0 GHz||8b/10b|
|PCIe 3.0||32 GB/s||8 GT/s||8.0 GHz||128b/130b|
|PCIe 4.0||64 GB/s||16 GT/s||16.0 GHz||128b/130b|
|PCIe 5.0||128 GB/s||32 GT/s||32.0 GHz||128b/130b|