Verilog Data Types
The data storage and transmission elements found in digital hardware are represented using a set of Verilog Hardware Description Language (HDL) data types. The purpose of Verilog HDL is to design digital hardware.
Data types in Verilog are divided into NETS and Registers. These data types differ in the way that they are assigned and hold values, and also they represent different hardware structures.
The Verilog HDL value set consists of four basic values:
|0||Logic zero or false|
|1||Logic one or true|
|x||Unknown logical value|
|z||High impedance of tristate gate|
- NETS – The nets variables represent the physical connection between structural entities. These variables do not store values (except trireg); they have the value of their drivers which changes continuously by the driving circuit. Some net data types are wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1 and trireg. Wire is the most frequently used type. A net data type must be used when a signal is:
- driven by the output of some device.
- declared as an input or in-out port.
- on the left-hand side of a continuous assignment.
- Registers – The register variables are used in procedural blocks which store values from one assignment to the next. An assignment statement in a procedure acts as a trigger that changes the value of the data storage element. Some register data types are: reg, integer, time and real. reg is the most frequently used type. Reg is used for describing logic, integer for loop variables and calculations, real in system modules, and time and real-time for storing simulation times in test benches.
- The reg variables are initialized to x at the start of the simulation. Any wire variable not connected to anything has the x value.
- The size of a register or wire may be specified during declaration.
- When the reg or wire size is more than one bit, then register and wire are declared as vectors.
Reference: DIGITAL ELECTRONICS – Atul P.Godse, Mrs. Deepali A. Godse