Vector Instruction Format in Vector Processors
Different Instruction formats are used by different vector processors. Vector instructions are generally specified by some fields. The main fields that are used in vector instruction set are given below:
- Operations Code (Opcode) –
The operation code must be specified to select the functional unit or to reconfigure a multi-functional unit to perform the specified operation dictated by this field. Usually, microcode control is used to set up the required resources.
Opcode – 0001 mnemonic – ADD operation – add the content of memory to the content of accumulator
Opcode – 0010 mnemonic – SUB operation – subtract the content of memory to the content of accumulator
Opcode – 1111 mnemonic – HLT operation – stop processing
- Base addresses –
For a memory reference instruction, the base addresses are needed for both source operands and result vectors. The designated vector registers must be specified in the instruction, if the operands and results are located in the vector register file, i.e., collection of registers.
ADD R1, R2
Here, R1 and R2 are the addresses of the register.
- Offset (or Displacement) –
This field is required to get the effective memory address of operand vector. The address offset relative to the base address should be specified. Using the base address and the offset (positive or negative), the effective address is calculated.
- Address Increment –
The address increment between the scalar elements of vector operand must be specified. Some computers, i.e., the increment is always 1. Some other computers, like TI-ASC, can have a variable increment, which offers higher flexibility in application.
R1 <- 400
Auto incr-R1 is incremented the value of R1 by 1.
R1 = 399
- Vector length –
The vector length (positive integer) is needed to determine the termination of a vector instruction.