The three outputs x1x2x3 from the 8 X 3 priority encoder are used to provide a vector address of the form 101x1x2x300. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority ?
Question 1 Explanation:
The priority preference for 8 X 3 priority encoder will be:
000 First 001 Second 010 Third 011 Fourth 100 Fifth 101 Sixth 110 Seventh 111 EighthAccording to question second highest priority vector address will be 10100100. i.e. 1010 0100. When we convert it to hexadecimal then it will be A4. So, option (B) is correct.
What will be the output at PORT1 if the following program is executed ? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT
Which of the following 8085 microprocessor hardware interrupt has the lowest priority?
Question 3 Explanation:
8085 microprocessor has 5 hardware interrupts. Named TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. The above order is decreasing in priority. So, option (D) is correct.
A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?
Question 4 Explanation:
Memory cycle time = 250 nsec memory is refreshed 32 times per msec i.e. Number of refreshes in 1 memory cycle (i.e in 250 nsec) = (32 * 250 * 10-9) / 10-3 = 8 * 10-3. Time taken for each refresh = 100 nsec Time taken for 8 * 10-3 refreshes = 8 * 10-3 * 100 * 10-9. = 8 * 10-10 Percentage of the memory cycle time used for refreshing : = (Time taken to refresh in 1 memory cycle / Total time) * 100 = (8 * 10-10 / 250 * 10-9) * 100 = 0.032 * 10 = 0.32 So, option (D) is correct.
A DMA controller transfers 32-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
Question 5 Explanation:
DMA controller transfers 32 bit(4 byte) words to memory(cycle stealing mode). Device transmits 4800 character per second (1 character = i byte) So, for 1 byte it will take 1 / 4800 sec. Since the controller transfers 4 byte in cycle stealing mode, it will take 4 * (1 / 4800) = 1 / 1200 sec. i.e. 1200 character will be transfered in cycle stealing mode and it is given that CPU is fetching and executing instructions at an average rate of one million instructions per second. slow down or cycle wasted % in DMA transfer = ( 1200 / 1000000) * 100 = 0.12 % So, option (B) is correct.
A CPU handles interrupt by executing interrupt service subroutine __________.
by checking interrupt register after execution of each instruction
by checking interrupt register at the end of the fetch cycle
whenever an interrupt is registered
by checking interrupt register at regular time interval
Question 6 Explanation:
A CPU handles interrupt by executing interrupt service subroutine by checking interrupt register after execution of each instruction. So, option (A) is correct.
Given the following set of prolog clauses : father(X, Y) : parent(X, Y), male(X), parent(Sally, Bob), parent(Jim, Bob), parent(Alice, Jane), parent(Thomas, Jane), male(Bob), male(Jim), female(Salley), female(Alice). How many atoms are matched to the variable ‘X’ before the query father(X, Jane) reports a Result ?
No option is correct.
Forward chaining systems are __________ where as backward chaining systems are __________.
Data driven, Data driven
Goal driven, Data driven
Data driven, Goal driven
Goal driven, Goal driven
Question 8 Explanation:
Forward chaining systems are data driven where as backward chaining systems are goal driven. So, option (C) is correct.
Match the following w.r.t. programming language:
No option is correct.
Question 9 Explanation:
- JAVA is statically object oriented language.
- Python is dynamic object oriented language.
- Prolog is non object oriented language.
- ADA is statically object oriented language.
The combination of an IP address and a port number is known as ___________.
subnet mask number
Question 10 Explanation:
There are 75 questions to complete.
My Personal Notes arrow_drop_up