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Types of Machine Instructions

Overview :
Based on operation performed, machine instructions can be divided into the following :

1. Data Transfer Instructions :

Instructions that transfer data from one location (Register/Memory) to another location (Register/Memory) without changing the data. Data transfer operations supported are as follows :

• LOAD :  Data transfers from memory to register.
• STORE :  Data transfers from register to memory.
• MOVE :  Data transfers from register to register.
• IN :  Transfers data from input device to register.
• OUT :  Transfers data from register to output device.
• PUSH :  Gets data from register or memory on to the top of the stack.
• POP :  Gets data from Top of the stack to memory or register.
• XCHG :  Exchanges the data between memory and registers.
• Arithmetic Instructions :
Performs an arithmetic operation such as addition, subtraction, multiplication, division, increment, decrement etc.
Example : ADD, SUB, MUL, DIV, INC, DEC etc.
• Logical Instructions :
Performs bit-wise logical operation such as AND, OR, Exclusive-OR, NOT, shift, rotate etc.
Example : AND, OR, NOT, XOR, SHL, SHR, ROL, ROR etc.
• Arithmetic and Logical Instructions :
Performs operations such as arithmetic shift left, arithmetic shift right.
Example : SAL, SAR etc.

3. Program Control Instructions :

-> Compare Test Instructions : To compare and test status flags we need support of condition code register. Condition Code Register (CCR) has following flag bits:

(i) 5 status bits : To indicate the situation after the arithmetic and logic operation.

• Carry flag (C) : It indicates a carry from an addition and borrow from a subtraction
• Overflow flag (V) : CPU sets ‘V’ flag to a logic ‘1’ when the result of an operation is beyond of the range that can be represented.
• Negative Flag (N) : It is also called as Sign flag. Indicates that whether previous result is negative or positive.
• Half Carry (H) : Used only for BCD (Binary Coded Decimal) operations.
• Zero Flag (Z) : Z bit is set to a logic ‘1’ when the result is ‘0’ otherwise Z=0. Note that zero is a positive number

(iii) One Stop Disable bit

-> Unconditional Branch Instructions : It causes an unconditional change of execution sequence to a new location. Example : JUMP, goto etc.

-> Conditional Branch Instructions : These instructions are used to examine the values stored in the condition code register to determine whether the specific code exists and to branch if it does. Examples :

• BL – Branch is Less than – (<)
• BGE – Branch is greater than equal to – (>=)
• BNE – Branch if not equal – (!=) etc.

-> Subroutines : It is a program fragment that lives in user space, performs a well-defined task if it is invoked by another user programs and returns control to the calling program when finished. Example : CALL, RET instructions. Subroutine is used for :

• Frequently used code segments
• Library routines

-> Halting and Interrupt instructions : They are as follows –

1. NOP Instruction :
Means no operation, causes no change in the processor state other than the advancement of the program counter. It can be used to synchronize timing.

2. HALT Instruction :
It brings a processor to an orderly halt, remaining in the idle state until restarted by interrupt, trace, reset or external action.

3. Interrupt Instructions :
It is a mechanism by which an I/O or an instruction can suspend the normal execution of the processor and get itself serviced. Generally, a particular task is assigned to that interrupt signal. In microprocessor interrupt are used for data transfer between peripheral devices and microprocessor. The instructions are –

• RESET –
It resets the processor, this may include any or all of setting registers to a initial value, setting program counter to initial location, clearing or setting interrupts, and sending reset signal to external devices.
• TRAP –
It is non-maskable and edge triggered interrupt. TRAP has the highest priority among vectored interrupt. In case of sudden power failure it executes an ISR and send the data from main memory to backup memory. It can be delayed using HOLD signal. They can be masked by resetting the microprocessor. There is no other way to mask it.
• INTR –
It is a level triggered and maskable interrupt. On receiving the instruction, CPU saves the address of next instruction on the stack and executes received instruction. it has the lowest priority. it can be disabled by resetting the microprocessor or by DI/SIM instruction.
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