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Translation Lookaside Buffer (TLB) in Paging

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  • Difficulty Level : Easy
  • Last Updated : 30 Oct, 2020
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In Operating System (Memory Management Technique : Paging), for each process page table will be created, which will contain Page Table Entry (PTE). This PTE will contain information like frame number (The address of main memory where we want to refer), and some other useful bits (e.g., valid/invalid bit, dirty bit, protection bit etc). This page table entry (PTE) will tell where in the main memory the actual page is residing. 

Now the question is where to place the page table, such that overall access time (or reference time) will be less. 

The problem initially was to fast access the main memory content based on address generated by CPU (i.e logical/virtual address). Initially, some people thought of using registers to store page table, as they are high-speed memory so access time will be less. 

The idea used here is, place the page table entries in registers, for each request generated from CPU (virtual address), it will be matched to the appropriate page number of the page table, which will now tell where in the main memory that corresponding page resides. Everything seems right here, but the problem is register size is small (in practical, it can accommodate maximum of 0.5k to 1k page table entries) and process size may be big hence the required page table will also be big (lets say this page table contains 1M entries), so registers may not hold all the PTE’s of Page table. So this is not a practical approach. 

To overcome this size issue, the entire page table was kept in main memory. but the problem here is two main memory references are required: 

  1. To find the frame number 
  2. To go to the address specified by frame number 

To overcome this problem a high-speed cache is set up for page table entries called a Translation Lookaside Buffer (TLB). Translation Lookaside Buffer (TLB) is nothing but a special cache used to keep track of recently used transactions. TLB contains page table entries that have been most recently used. Given a virtual address, the processor examines the TLB if a page table entry is present (TLB hit), the frame number is retrieved and the real address is formed. If a page table entry is not found in the TLB (TLB miss), the page number is used as index while processing page table. TLB first checks if the page is already in main memory, if not in main memory a page fault is issued then the TLB is updated to include the new page entry. 


Steps in TLB hit: 

  1. CPU generates virtual (logical) address. 
  2. It is checked in TLB (present). 
  3. Corresponding frame number is retrieved, which now tells where in the main memory page lies. 

Steps in TLB miss: 

  1. CPU generates virtual (logical) address. 
  2. It is checked in TLB (not present). 
  3. Now the page number is matched to page table residing in main memory (assuming page table contains all PTE). 
  4. Corresponding frame number is retrieved, which now tells where in the main memory page lies. 
  5. The TLB is updated with new PTE (if space is not there, one of the replacement technique comes into picture i.e either FIFO, LRU or MFU etc). 

Effective memory access time(EMAT) : TLB is used to reduce effective memory access time as it is a high speed associative cache. 
EMAT = h*(c+m) + (1-h)*(c+2m) 
where, h = hit ratio of TLB 
m = Memory access time 
c = TLB access time 


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