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Timing diagram of MOV Instruction in Microprocessor

Last Updated : 31 May, 2022
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Problem – Draw the timing diagram of the given instruction in 8085,


Given instruction copy the contents of the source register into the destination register and the contents of the source register are not altered.


Opcode: MOV 
Operand: B and C 

Bis is the destination register and C is the source register whose contents need to be transferred to the destination register. Algorithm – The instruction MOV B, C is of 1 byte; therefore the complete instruction will be stored in a single memory address. For example:

2000: MOV B, C 

Only opcode fetching is required for this instruction and thus we need 4 T states for the timing diagram. For the opcode fetch the IO/M (low active) = 0, S1 = 1 and S0 = 1. The timing diagram of MOV instruction is shown below:  

In Opcode fetch ( t1-t4 T states):

  • 00 – lower bit of address where the opcode is stored, i.e., 00.
  • 20 – higher bit of address where the opcode is stored, i.e., 20.
  • ALE – provides signal for multiplexed address and data bus. Only in t1 is it used as an address bus to fetch a lower bit of address otherwise it will be used as the data bus.
  • RD (low active) – signal is 1 in t1 & t4 as no data is read by the microprocessor. Signal is 0 in t2 & t3 because here the data is read by a microprocessor.
  • WR (low active) – signal is 1 throughout, no data is written by a microprocessor.
  • IO/M (low active) – signal is 1 throughout because the operation is performing on memory.
  • S0 and S1 – both are 1 in case of opcode fetching.

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