Synchronous Data Transfer in Computer Organization
In Synchronous data transfer, the sending and receiving units are enabled with same clock signal. It is possible between two units when each of them knows the behavior of the other. The master performs a sequence of instructions for data transfer in a predefined order. All these actions are synchronized with the common clock. The master is designed to supply the data at a time when the slave is definitely ready for it. Usually, the master will introduce sufficient delay to take into account the slow response of the slave, without any request from the slave.
The master does not expect any acknowledgment signal from the slave when data is sent by the master to the slave. Similarly, when data from the slave is read by the master, neither the slave informs that the data has been placed on the data bus nor the master acknowledges that the data has been read. Both the master and slave perform their own task of transferring data at a designed clock period. Since both devices know the behavior (response time) of each other, no difficulty arises.
Prior to transferring data, the master must logically select the slave either by sending slave’s address or sending “device select” signal to the slave. But there is no acknowledgment signal from the slave to the master if the device is selected.
Timing diagram of the synchronous read operation is given below:
In this timing diagram, the master first places slave’s address in the address bus and read signal in the control line at the falling edge of the clock. The entire read operation is over in one clock period.
- The design procedure is easy. The master does not wait for any acknowledges signal from the slave, though the master waits for a time equal to slave’s response time.
- The slave does not generate an acknowledge signal, though it obeys the timing rules as per the protocol set by the master or system designer.
- If a slow speed unit connected to a common bus, it can degrade the overall rate of transfer in the system.
- If the slave operates at a slow speed, the master will be idle for some time during data transfer and vice versa.
Timing: In synchronous data transfer, the data transfer is synchronized with a common clock signal that is generated by the sending device and used by both the sending and receiving devices. This ensures that both devices are in sync and ready to receive or transmit data at the same time.
Data transfer modes: Synchronous data transfer can be done using either the parallel or serial mode of data transfer. In parallel data transfer, multiple bits of data are transferred simultaneously, while in serial data transfer, data is transferred bit-by-bit using a single data line.
Handshaking: Synchronous data transfer typically involves some form of handshaking between the sending and receiving devices to ensure that the data is transferred correctly. This can involve the use of signals such as Acknowledge (ACK) and Ready (RDY), which indicate that the receiving device is ready to receive or that the sending device has completed the transfer.
Data rate: The data transfer rate in synchronous data transfer is typically limited by the clock frequency and the number of bits that can be transferred in a single clock cycle. However, synchronous data transfer can be faster than asynchronous data transfer because there is no need to add extra bits for synchronization.
Transmission line: In synchronous data transfer, the transmission line used to transfer data must be properly designed and matched to the impedance of the devices to ensure that data is not lost due to reflections.
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