Pipelined architecture with its diagram

Pipeline Processor consists of a sequence of m data-processing circuits, called stages or segments, which collectively perform a single operation on a stream of data operands passing through them. Some processing takes place in each stage, but a final result is obtained only after an operand set has passed through the entire pipeline. As shown in figure, a stage S_(i) contains a multiword input register or latch R_(i), and a datapath circuit C_(i), that is usually combinational. The R_(i)‘s hold partially processed results as they move through the pipeline; they also serve as buffers that prevent neighbouring stages from interfering with one another.

A common clock signal causes the R_(i)‘s to change state synchronously. Each R_(i)‘s to change state synchronously. Each R_(i) receives a new set of input data D_(i-1) from the preceding stage S_(i-1) except for R₍₁₎ whose data is supplied from an external source. D_(i-1) represents the results computed by C_(i-1) during the preceding clock period. Once D_(i-1) has been loaded into R_(i), C_(i) proceeds to D_(i-1) to computer a new data set D_(i). Thus in each clock period, every stage transfers its previous results to the next stage and computers a new set of results.