Prerequisite – Paging, Page table entries, Segmentation
Most of the Operating Systems implement a separate pagetable for each process, i.e. for ‘n’ number of processes running on a Multiprocessing/ Timesharing operating system, there are ‘n’ number of pagetables stored in the memory. Sometimes when a process is very large in size and it occupies virtual memory then with the size of the process, it’s pagetable size also increases substantially.
Example: A process of size 2 GB with: Page size = 512 Bytes Size of page table entry = 4 Bytes, then Number of pages in the process = 2 GB / 512 B = 222 PageTable Size = 222 * 22 = 224 bytes
Through this example, it can be concluded that for multiple processes running simultaneously in an OS, a considerable part of memory is occupied by pagetables only.
Operating Systems also incorporate multilevel paging schemes which further increase the space requirement for storing the page tables and a large amount of memory is invested in storing them. The amount of memory occupied by the page tables can turn out to be a huge overhead and is always unacceptable as main memory is always a scarce-resource. Various efforts are made to utilize the memory efficiently and to maintain a good balance in the level of multi programming and efficient CPU utilization.
Inverted Page Table –
An alternate approach is to use the Inverted Page Table structure that consists of one page table entry for every frame of the main memory. So the number of page table entries in the Inverted Page Table reduces to the number of frames in physical memory and a single page table is used to represent the paging information of all the processes.
Through inverted page table, the overhead of storing an individual pagetable for every process gets eliminated and only a fixed portion of memory is required to store the paging information of all the processes together. This technique is called as inverted paging as the indexing is done with respect to the frame number instead of the logical page number. Each entry in the page table contains the following fields.
- Page number – It specifies the page number range of the logical address.
- Process id – An inverted page table contains the address space information of all the processes in execution. Since two different processes can have similar set of virtual addresses, it becomes necessary in Inverted Page Table to store a process Id of each process to identify it’s address space uniquely. This is done by using the combination of PId and Page Number. So this Process Id acts as an address space identifier and ensures that a virtual page for a particular process is mapped correctly to the corresponding physical frame.
- Control bits – These bits are used to store extra paging-related information. These include the valid bit, dirty bit, reference bits, protection and locking information bits.
- Chained pointer – It may be possible sometime that two or more processes share a part of main memory. In this case, two or more logical pages map to same Page Table Entry then a chaining pointer is used to map the details of these logical pages to the root page table.
Working – The operation of an inverted page table is shown below.
The virtual address generated by the CPU contains the fields
Examples – The Inverted Pagetable and its variations are implemented in various systems like PowerPC, UltraSPARC and the IA-64 architecture. An implementation of Mach operating system on the RT-PC also uses this technique.
Advantages and Disadvantages:
- Reduced memory space –
Inverted Pagetables typically reduces the amount of memory required to store the page tables to a size bound of physical memory. The maximum number of entries could be the number of page frames in the physical memory.
- Longer lookup time –
Inverted Pagetables are sorted in order of frame number but the memory look-up takes place with respect to the virtual address, so, it usually takes a longer time to find the appropriate entry but often these pagetables are implemented using hash data structures for a faster lookup.
- Difficult shared memory implementation –
As the Inverted Page Table stores a single entry for each frame, it becomes difficult to implement the shared memory in the page tables. Chaining techniques are used to map more than one virtual address to the entry specified in order of frame number.
If you like GeeksforGeeks and would like to contribute, you can also write an article using contribute.geeksforgeeks.org or mail your article to firstname.lastname@example.org. See your article appearing on the GeeksforGeeks main page and help other Geeks.
Please Improve this article if you find anything incorrect by clicking on the "Improve Article" button below.