Direction for questions 63 to 64:
Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.
Instruction Operation Instruction Size(in words)
MOV R1,5000; R1 ¬ Memory 2
MOV R2, (R1); R2 ¬ Memory[(R1)] 1
ADD R2, R3; R2 ¬ R2 + R3 1
MOV 6000, R2; Memory  ¬ R2 2
HALT Machine halts 1
Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be
Instructions size are given in words. So first instruction will take 2 words i.e 8 bytes(as 32 bit byte addressable, word size will be 32 bit ) so on for 2nd instruction 4 byte, for 3rd 4 bytes, 4th 8 bytes..5th 4 bytes. As 1st instruction starts from 1000 and the size is 8 bytes second instruction address will be 1008, like wise 3rd instruction address will be 1012,4th instruction address 1016,5th instruction address 1024 and halt instruction address will be 1028. As an interrupt occurs executing the HALT instruction, the return address (in decimal) saved in the stack will be the address of the halt instruction ..so answer is 1028.
Note - If interrupt occur, then value of PC will be return address of that instruction after HALT.