ISRO | ISRO CS 2020 | Question 70

A non-pipelined CPU has 12 general purpose registers (R0, R1, R2, ..... R12). Following operation are supported:

ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr 

MUL operations takes two clock cycles, ADD takes one clock cycle. Calculate minimum number of clock cycles required to compute the value of the expression XY + XYZ + YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 and contents of these registers must not be modified.