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ISRO | ISRO CS 2016 | Question 16

  • Last Updated : 19 Nov, 2018

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a
pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls
in the pipeline. The speedup achieved in this pipelined processor is
(A) 3.2
(B) 3.0
(C) 2.2
(D) 2.0

Answer: (A)

Explanation: Refer: GATE-CS-2015 (Set 1) | Question 65
So, option (A) is correct.

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