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ISRO | ISRO CS 2014 | Question 1
Consider a 33 MHz CPU based system. What is the number of wait states required if it is interfaced with a 60 ns memory? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.
(A)
0
(B)
1
(C)
2
(D)
3
Answer
Please comment below if you find anything wrong in the above post
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