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ISRO | ISRO CS 2014 | Question 1
  • Last Updated : 19 Nov, 2018

Consider a 33 MHz CPU based system. What is the number of wait states required if it is interfaced with a 60 ns memory? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.
(A) 0
(B) 1
(C) 2
(D) 3


Answer: (D)

Explanation: A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond.

Total memory access time = 60 ns + 10 ns = 70 ns.

Given, CPU frequency = 33 MHz
So,
1 clock time = 1 / (33 MHz) = (1/33)*10-6 = 30.30 ns.

Therefore,
Total number of wait states = Total number of cycle needed = 70 ns / (30.30 ns) = 2.31 ≈ 3 cycles.

So, option (D) is correct.

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