Skip to content
Related Articles

Related Articles

ISRO | ISRO CS 2007 | Question 3
  • Last Updated : 20 Nov, 2018

The circuit shown in the given figure is a


(A) full adder
(B) full subtracter

(C) shift register
(D) decade counter


Answer: (B)

Explanation: The circuit shown in the given figure is a full subtractor.

Refer: Digital Logic | Full Subtractor

Option (B) is correct.

Quiz of this Question

My Personal Notes arrow_drop_up
Recommended Articles
Page :